• Lab Rules & Policies (Spring/Summer 2025)
• Lab submission template (Spring/Summer 2025): MS Word & PDF
• Honorlock and Lab Quiz info
• Templates of Legends for Switches and LEDs
• Summer 2025 Parts List (R0)
  • As soon as you open your purchased lab parts, for documentation purposes, take picture of all of the parts in your kit (chips, PCB, breadboard, cables, etc) and include these images in your Pre-Lab Reports for Lab 0.
  • Parts List prior to fall 2023
• DE10-Lite Pins (R0)
  
• OOTB EEL3701 Connection Guide
• Suggestions for Debugging your PLD PCB
• DE10-Lite User Manual
  
• To use the DE10-lite in Quartus, do the following:
       - Select "Assignment"
       - Select "Device" and then select the "Board" tab towards the top of the screen
       - Change the family to "MAX 10", and select "MAX 10 DE10 - Lite".
• The DE10-Lite uses a Max 10 FPGA Device, 10M50DAF484C6GES
  
• Default pof for DE10-Lite (to restore to default config)
  
  MAX 10 Documentation
  
  • Max 10 Overview
    
  • Max 10 Architecture
    
  • Max 10 User Embedded RAM/ROM (1-port/2-port) Memory
    
  • Max 10 User Flash Memory
    

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  Prior to Fall 2023
  • We were using a Max 10 FPGA Device, 10M02SCU169C8G.
    
    • Select Family: MAX 10 (DA/DF/DC/SA/SC)
      
    • Select Device: 10M02SCU169C8G
      
  
  Prior to that we were usinga MAX V
  
  • We previously used a Max V PLD, 5M570ZT100C5N.
    
    • In Quartus, select Family: MAX V and Device: 5M570ZT100C5
      
    • Max V CPLD documentation (handbook - May 2011)

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Mon, 7 July
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