Fitter report for f15_per4
Tue Sep 08 11:04:34 2015
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Non-Global High Fan-Out Signals
 13. Interconnect Usage Summary
 14. LAB Macrocells
 15. Logic Cell Interconnection
 16. Fitter Device Options
 17. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; Fitter Summary                                                       ;
+-----------------------+----------------------------------------------+
; Fitter Status         ; Successful - Tue Sep 08 11:04:34 2015        ;
; Quartus II Version    ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name         ; f15_per4                                     ;
; Top-level Entity Name ; f15_per4                                     ;
; Family                ; MAX3000A                                     ;
; Device                ; EPM3064ALC44-10                              ;
; Timing Models         ; Final                                        ;
; Total macrocells      ; 1 / 64 ( 2 % )                               ;
; Total pins            ; 8 / 34 ( 24 % )                              ;
+-----------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                              ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option                                                                     ; Setting         ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device                                                                     ; EPM3064ALC44-10 ;               ;
; Fitter Effort                                                              ; Standard Fit    ; Auto Fit      ;
; Use smart compilation                                                      ; Off             ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On              ; On            ;
; Enable compact report table                                                ; Off             ; Off           ;
; Use TimeQuest Timing Analyzer                                              ; Off             ; Off           ;
; Optimize Timing for ECOs                                                   ; Off             ; Off           ;
; Regenerate full fit report during ECO compiles                             ; Off             ; Off           ;
; Optimize IOC Register Placement for Timing                                 ; On              ; On            ;
; Limit to One Fitting Attempt                                               ; Off             ; Off           ;
; Fitter Initial Placement Seed                                              ; 1               ; 1             ;
; Slow Slew Rate                                                             ; Off             ; Off           ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off             ; Off           ;
; Use Best Effort Settings for Compilation                                   ; Off             ; Off           ;
+----------------------------------------------------------------------------+-----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in //mil.ufl.edu/wwwroot/mil.ufl.edu/3701/examples/quartus/f15_per4/f15_per4.pin.


+-----------------------------------------------------+
; Fitter Resource Usage Summary                       ;
+-----------------------------------+-----------------+
; Resource                          ; Usage           ;
+-----------------------------------+-----------------+
; Logic cells                       ; 1 / 64 ( 2 % )  ;
; Registers                         ; 0 / 64 ( 0 % )  ;
; Number of pterms used             ; 2               ;
; User inserted logic elements      ; 0               ;
; I/O pins                          ; 8 / 34 ( 24 % ) ;
;     -- Clock pins                 ; 0 / 2 ( 0 % )   ;
;     -- Dedicated input pins       ; 0 / 2 ( 0 % )   ;
; Global signals                    ; 0               ;
; Shareable expanders               ; 0 / 64 ( 0 % )  ;
; Parallel expanders                ; 0 / 60 ( 0 % )  ;
; Cells using turbo bit             ; 1 / 64 ( 2 % )  ;
; Maximum fan-out node              ; inst1~1         ;
; Maximum fan-out                   ; 1               ;
; Highest non-global fan-out signal ; inst1~1         ;
; Highest non-global fan-out        ; 1               ;
; Total fan-out                     ; 4               ;
; Average fan-out                   ; 0.44            ;
+-----------------------------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                ;
+------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; I/O Standard ; Location assigned by ;
+------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; A    ; 4     ; --       ; 1   ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; Fitter               ;
; B    ; 40    ; --       ; 4   ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; Fitter               ;
; C_L  ; 41    ; --       ; 4   ; 1                     ; 0                  ; no     ; 3.3-V LVTTL  ; Fitter               ;
+------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                              ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
; Y    ; 12    ; --       ; 1   ; no              ; no             ; no         ; no            ; 3.3-V LVTTL  ; Fitter               ; 10 pF ; -                    ; -                   ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+


+-------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                      ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; User Assignment ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; 1        ; 0          ; --       ; GND+           ;        ;              ;         ;                 ;
; 2        ; 1          ; --       ; GND+           ;        ;              ;         ;                 ;
; 3        ; 2          ; --       ; VCCINT         ; power  ;              ; 3.3V    ;                 ;
; 4        ; 3          ; --       ; A              ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 5        ; 4          ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 6        ; 5          ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 7        ; 6          ; --       ; TDI            ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 8        ; 7          ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 9        ; 8          ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 10       ; 9          ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 11       ; 10         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 12       ; 11         ; --       ; Y              ; output ; 3.3-V LVTTL  ;         ; N               ;
; 13       ; 12         ; --       ; TMS            ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 14       ; 13         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 15       ; 14         ; --       ; VCCIO          ; power  ;              ; 3.3V    ;                 ;
; 16       ; 15         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 17       ; 16         ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 18       ; 17         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 19       ; 18         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 20       ; 19         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 21       ; 20         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 22       ; 21         ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 23       ; 22         ; --       ; VCCINT         ; power  ;              ; 3.3V    ;                 ;
; 24       ; 23         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 25       ; 24         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 26       ; 25         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 27       ; 26         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 28       ; 27         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 29       ; 28         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 30       ; 29         ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 31       ; 30         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 32       ; 31         ; --       ; TCK            ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 33       ; 32         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 34       ; 33         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 35       ; 34         ; --       ; VCCIO          ; power  ;              ; 3.3V    ;                 ;
; 36       ; 35         ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 37       ; 36         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 38       ; 37         ; --       ; TDO            ; output ; 3.3-V LVTTL  ;         ; N               ;
; 39       ; 38         ; --       ; RESERVED       ;        ;              ;         ;                 ;
; 40       ; 39         ; --       ; B              ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 41       ; 40         ; --       ; C_L            ; input  ; 3.3-V LVTTL  ;         ; N               ;
; 42       ; 41         ; --       ; GND            ; gnd    ;              ;         ;                 ;
; 43       ; 42         ; --       ; GND+           ;        ;              ;         ;                 ;
; 44       ; 43         ; --       ; GND+           ;        ;              ;         ;                 ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-----------------------------------------------+
; Output Pin Default Load For Reported TCO      ;
+--------------+-------+------------------------+
; I/O Standard ; Load  ; Termination Resistance ;
+--------------+-------+------------------------+
; 3.3-V LVTTL  ; 10 pF ; Not Available          ;
; 3.3-V LVCMOS ; 10 pF ; Not Available          ;
; 3.3-V PCI    ; 10 pF ; 25 Ohm (Parallel)      ;
; 2.5 V        ; 10 pF ; Not Available          ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+-------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                               ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |f15_per4                  ; 1          ; 8    ; |f15_per4           ; work         ;
+----------------------------+------------+------+---------------------+--------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+---------+-----------------------+
; Name    ; Fan-Out               ;
+---------+-----------------------+
; B       ; 1                     ;
; A       ; 1                     ;
; C_L     ; 1                     ;
; inst1~1 ; 1                     ;
+---------+-----------------------+


+----------------------------------------------+
; Interconnect Usage Summary                   ;
+----------------------------+-----------------+
; Interconnect Resource Type ; Usage           ;
+----------------------------+-----------------+
; Output enables             ; 0 / 6 ( 0 % )   ;
; PIA buffers                ; 3 / 144 ( 2 % ) ;
+----------------------------+-----------------+


+----------------------------------------------------------------------+
; LAB Macrocells                                                       ;
+----------------------------------------+-----------------------------+
; Number of Macrocells  (Average = 0.25) ; Number of LABs  (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0                                      ; 3                           ;
; 1                                      ; 1                           ;
+----------------------------------------+-----------------------------+


+---------------------------------------+
; Logic Cell Interconnection            ;
+-----+------------+-----------+--------+
; LAB ; Logic Cell ; Input     ; Output ;
+-----+------------+-----------+--------+
;  A  ; LC1        ; A, B, C_L ; Y      ;
+-----+------------+-----------+--------+


+---------------------------------------------------------------+
; Fitter Device Options                                         ;
+----------------------------------------------+----------------+
; Option                                       ; Setting        ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
; Enable device-wide reset (DEV_CLRn)          ; Off            ;
; Enable device-wide output enable (DEV_OE)    ; Off            ;
; Enable INIT_DONE output                      ; Off            ;
; Configuration scheme                         ; Passive Serial ;
; Security bit                                 ; Off            ;
; Base pin-out file on sameframe device        ; Off            ;
+----------------------------------------------+----------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
    Info: Processing started: Tue Sep 08 11:04:33 2015
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off f15_per4 -c f15_per4
Info: Selected device EPM3064ALC44-10 for design "f15_per4"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 183 megabytes
    Info: Processing ended: Tue Sep 08 11:04:34 2015
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


