Analysis & Synthesis report for thur_per9
Thu Sep 02 16:47:39 2010
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 02 16:47:39 2010        ;
; Quartus II Version          ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name               ; thur_per9                                    ;
; Top-level Entity Name       ; thur_per9                                    ;
; Family                      ; MAX7000S                                     ;
; Total macrocells            ; 1                                            ;
; Total pins                  ; 4                                            ;
+-----------------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option                                                                     ; Setting         ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device                                                                     ; EPM7064SLC44-10 ;               ;
; Top-level entity name                                                      ; thur_per9       ; thur_per9     ;
; Family name                                                                ; MAX7000S        ; Stratix II    ;
; Use Generated Physical Constraints File                                    ; Off             ;               ;
; Use smart compilation                                                      ; Off             ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On              ; On            ;
; Enable compact report table                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                        ; Off             ; Off           ;
; Preserve fewer node names                                                  ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                                  ; Off             ; Off           ;
; Verilog Version                                                            ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                               ; VHDL_1993       ; VHDL_1993     ;
; State Machine Processing                                                   ; Auto            ; Auto          ;
; Safe State Machine                                                         ; Off             ; Off           ;
; Extract Verilog State Machines                                             ; On              ; On            ;
; Extract VHDL State Machines                                                ; On              ; On            ;
; Ignore Verilog initial constructs                                          ; Off             ; Off           ;
; Iteration limit for constant Verilog loops                                 ; 5000            ; 5000          ;
; Iteration limit for non-constant Verilog loops                             ; 250             ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On              ; On            ;
; Parallel Synthesis                                                         ; On              ; On            ;
; NOT Gate Push-Back                                                         ; On              ; On            ;
; Power-Up Don't Care                                                        ; On              ; On            ;
; Remove Duplicate Registers                                                 ; On              ; On            ;
; Ignore CARRY Buffers                                                       ; Off             ; Off           ;
; Ignore CASCADE Buffers                                                     ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                      ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                                  ; Off             ; Off           ;
; Ignore LCELL Buffers                                                       ; Auto            ; Auto          ;
; Ignore SOFT Buffers                                                        ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                             ; Off             ; Off           ;
; Optimization Technique                                                     ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                       ; On              ; On            ;
; Auto Logic Cell Insertion                                                  ; On              ; On            ;
; Parallel Expander Chain Length                                             ; 4               ; 4             ;
; Auto Parallel Expanders                                                    ; On              ; On            ;
; Auto Open-Drain Pins                                                       ; On              ; On            ;
; Auto Resource Sharing                                                      ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell                                               ; 100             ; 100           ;
; Use LogicLock Constraints during Resource Balancing                        ; On              ; On            ;
; Ignore translate_off and synthesis_off directives                          ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                         ; On              ; On            ;
; HDL message level                                                          ; Level2          ; Level2        ;
; Suppress Register Optimization Related Messages                            ; Off             ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000            ; 5000          ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100             ; 100           ;
; Block Design Naming                                                        ; Auto            ; Auto          ;
; Synthesis Effort                                                           ; Auto            ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On              ; On            ;
; Analysis & Synthesis Message Level                                         ; Medium          ; Medium        ;
; Disable Register Merging Across Hierarchies                                ; Auto            ; Auto          ;
+----------------------------------------------------------------------------+-----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; File Name with User-Entered Path                                               ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                   ;
+--------------------------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; //mil.ufl.edu/web/3701/examples/quartus/intro_examples/thur_per9/thur_per9.bdf ; yes             ; User Block Diagram/Schematic File  ; //mil.ufl.edu/web/3701/examples/quartus/intro_examples/thur_per9/thur_per9.bdf ;
+--------------------------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 1                    ;
; Total registers      ; 0                    ;
; I/O pins             ; 4                    ;
; Maximum fan-out node ; inst1~1              ;
; Maximum fan-out      ; 1                    ;
; Total fan-out        ; 4                    ;
; Average fan-out      ; 0.80                 ;
+----------------------+----------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                 ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |thur_per9                 ; 1          ; 4    ; |thur_per9          ; work         ;
+----------------------------+------------+------+---------------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
    Info: Processing started: Thu Sep 02 16:47:34 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off thur_per9 -c thur_per9
Info: Found 1 design units, including 1 entities, in source file thur_per9.bdf
    Info: Found entity 1: thur_per9
Info: Elaborating entity "thur_per9" for the top level hierarchy
Info: Implemented 5 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 192 megabytes
    Info: Processing ended: Thu Sep 02 16:47:39 2010
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:03


