|tt_RAMx
RAM_Enable <= 37.DB_MAX_OUTPUT_PORT_TYPE
ADDR[0] => lpm_ram_io1:inst1.address[0]
ADDR[1] => lpm_ram_io1:inst1.address[1]
ADDR[2] => lpm_ram_io1:inst1.address[2]
ADDR[3] => lpm_ram_io1:inst1.address[3]
ADDR[4] => lpm_ram_io1:inst1.address[4]
ADDR[5] => lpm_ram_io1:inst1.address[5]
ADDR[6] => lpm_ram_io1:inst1.address[6]
ADDR[7] => lpm_ram_io1:inst1.address[7]
ADDR[8] => lpm_ram_io1:inst1.address[8]
ADDR[9] => lpm_ram_io1:inst1.address[9]
ADDR[10] => lpm_ram_io1:inst1.address[10]
ADDR[11] => lpm_ram_io1:inst1.address[11]
ADDR[12] => 36.IN0
ADDR[13] => 37.IN2
ADDR[14] => 37.IN1
ADDR[15] => 37.IN0
DATA[0] <= lpm_ram_io1:inst1.dio[0]
DATA[1] <= lpm_ram_io1:inst1.dio[1]
DATA[2] <= lpm_ram_io1:inst1.dio[2]
DATA[3] <= lpm_ram_io1:inst1.dio[3]
DATA[4] <= lpm_ram_io1:inst1.dio[4]
DATA[5] <= lpm_ram_io1:inst1.dio[5]
DATA[6] <= lpm_ram_io1:inst1.dio[6]
DATA[7] <= lpm_ram_io1:inst1.dio[7]
RAM_WE => lpm_ram_io1:inst1.we
RAM_OE => lpm_ram_io1:inst1.outenab


|tt_RAMx|lpm_ram_io1:inst1
address[0] => lpm_ram_io:lpm_ram_io_component.address[0]
address[1] => lpm_ram_io:lpm_ram_io_component.address[1]
address[2] => lpm_ram_io:lpm_ram_io_component.address[2]
address[3] => lpm_ram_io:lpm_ram_io_component.address[3]
address[4] => lpm_ram_io:lpm_ram_io_component.address[4]
address[5] => lpm_ram_io:lpm_ram_io_component.address[5]
address[6] => lpm_ram_io:lpm_ram_io_component.address[6]
address[7] => lpm_ram_io:lpm_ram_io_component.address[7]
address[8] => lpm_ram_io:lpm_ram_io_component.address[8]
address[9] => lpm_ram_io:lpm_ram_io_component.address[9]
address[10] => lpm_ram_io:lpm_ram_io_component.address[10]
address[11] => lpm_ram_io:lpm_ram_io_component.address[11]
we => lpm_ram_io:lpm_ram_io_component.we
outenab => lpm_ram_io:lpm_ram_io_component.outenab
dio[0] <= lpm_ram_io:lpm_ram_io_component.dio[0]
dio[1] <= lpm_ram_io:lpm_ram_io_component.dio[1]
dio[2] <= lpm_ram_io:lpm_ram_io_component.dio[2]
dio[3] <= lpm_ram_io:lpm_ram_io_component.dio[3]
dio[4] <= lpm_ram_io:lpm_ram_io_component.dio[4]
dio[5] <= lpm_ram_io:lpm_ram_io_component.dio[5]
dio[6] <= lpm_ram_io:lpm_ram_io_component.dio[6]
dio[7] <= lpm_ram_io:lpm_ram_io_component.dio[7]


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component
dio[0] <= datatri[0]
dio[1] <= datatri[1]
dio[2] <= datatri[2]
dio[3] <= datatri[3]
dio[4] <= datatri[4]
dio[5] <= datatri[5]
dio[6] <= datatri[6]
dio[7] <= datatri[7]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
address[8] => altram:sram.address[8]
address[9] => altram:sram.address[9]
address[10] => altram:sram.address[10]
address[11] => altram:sram.address[11]
outenab => altr_temp~0.IN0
outenab => datatri[7]~0.IN0
memenab => altr_temp~2.IN1
memenab => datatri[7]~0.IN1
we => altr_temp~1.IN0


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram
we => real_we[1].IN1
we => real_we[0].IN1
data[0] => segment[1][0].DATAIN
data[0] => segment[0][0].DATAIN
data[1] => segment[1][1].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[1][2].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[1][3].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[1][4].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[1][5].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[1][6].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[1][7].DATAIN
data[7] => segment[0][7].DATAIN
address[0] => segment[1][7].WADDR
address[0] => segment[1][7].RADDR
address[0] => segment[1][6].WADDR
address[0] => segment[1][6].RADDR
address[0] => segment[1][5].WADDR
address[0] => segment[1][5].RADDR
address[0] => segment[1][4].WADDR
address[0] => segment[1][4].RADDR
address[0] => segment[1][3].WADDR
address[0] => segment[1][3].RADDR
address[0] => segment[1][2].WADDR
address[0] => segment[1][2].RADDR
address[0] => segment[1][1].WADDR
address[0] => segment[1][1].RADDR
address[0] => segment[1][0].WADDR
address[0] => segment[1][0].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[1][7].WADDR1
address[1] => segment[1][7].RADDR1
address[1] => segment[1][6].WADDR1
address[1] => segment[1][6].RADDR1
address[1] => segment[1][5].WADDR1
address[1] => segment[1][5].RADDR1
address[1] => segment[1][4].WADDR1
address[1] => segment[1][4].RADDR1
address[1] => segment[1][3].WADDR1
address[1] => segment[1][3].RADDR1
address[1] => segment[1][2].WADDR1
address[1] => segment[1][2].RADDR1
address[1] => segment[1][1].WADDR1
address[1] => segment[1][1].RADDR1
address[1] => segment[1][0].WADDR1
address[1] => segment[1][0].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[1][7].WADDR2
address[2] => segment[1][7].RADDR2
address[2] => segment[1][6].WADDR2
address[2] => segment[1][6].RADDR2
address[2] => segment[1][5].WADDR2
address[2] => segment[1][5].RADDR2
address[2] => segment[1][4].WADDR2
address[2] => segment[1][4].RADDR2
address[2] => segment[1][3].WADDR2
address[2] => segment[1][3].RADDR2
address[2] => segment[1][2].WADDR2
address[2] => segment[1][2].RADDR2
address[2] => segment[1][1].WADDR2
address[2] => segment[1][1].RADDR2
address[2] => segment[1][0].WADDR2
address[2] => segment[1][0].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[1][7].WADDR3
address[3] => segment[1][7].RADDR3
address[3] => segment[1][6].WADDR3
address[3] => segment[1][6].RADDR3
address[3] => segment[1][5].WADDR3
address[3] => segment[1][5].RADDR3
address[3] => segment[1][4].WADDR3
address[3] => segment[1][4].RADDR3
address[3] => segment[1][3].WADDR3
address[3] => segment[1][3].RADDR3
address[3] => segment[1][2].WADDR3
address[3] => segment[1][2].RADDR3
address[3] => segment[1][1].WADDR3
address[3] => segment[1][1].RADDR3
address[3] => segment[1][0].WADDR3
address[3] => segment[1][0].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[1][7].WADDR4
address[4] => segment[1][7].RADDR4
address[4] => segment[1][6].WADDR4
address[4] => segment[1][6].RADDR4
address[4] => segment[1][5].WADDR4
address[4] => segment[1][5].RADDR4
address[4] => segment[1][4].WADDR4
address[4] => segment[1][4].RADDR4
address[4] => segment[1][3].WADDR4
address[4] => segment[1][3].RADDR4
address[4] => segment[1][2].WADDR4
address[4] => segment[1][2].RADDR4
address[4] => segment[1][1].WADDR4
address[4] => segment[1][1].RADDR4
address[4] => segment[1][0].WADDR4
address[4] => segment[1][0].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[1][7].WADDR5
address[5] => segment[1][7].RADDR5
address[5] => segment[1][6].WADDR5
address[5] => segment[1][6].RADDR5
address[5] => segment[1][5].WADDR5
address[5] => segment[1][5].RADDR5
address[5] => segment[1][4].WADDR5
address[5] => segment[1][4].RADDR5
address[5] => segment[1][3].WADDR5
address[5] => segment[1][3].RADDR5
address[5] => segment[1][2].WADDR5
address[5] => segment[1][2].RADDR5
address[5] => segment[1][1].WADDR5
address[5] => segment[1][1].RADDR5
address[5] => segment[1][0].WADDR5
address[5] => segment[1][0].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[1][7].WADDR6
address[6] => segment[1][7].RADDR6
address[6] => segment[1][6].WADDR6
address[6] => segment[1][6].RADDR6
address[6] => segment[1][5].WADDR6
address[6] => segment[1][5].RADDR6
address[6] => segment[1][4].WADDR6
address[6] => segment[1][4].RADDR6
address[6] => segment[1][3].WADDR6
address[6] => segment[1][3].RADDR6
address[6] => segment[1][2].WADDR6
address[6] => segment[1][2].RADDR6
address[6] => segment[1][1].WADDR6
address[6] => segment[1][1].RADDR6
address[6] => segment[1][0].WADDR6
address[6] => segment[1][0].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[1][7].WADDR7
address[7] => segment[1][7].RADDR7
address[7] => segment[1][6].WADDR7
address[7] => segment[1][6].RADDR7
address[7] => segment[1][5].WADDR7
address[7] => segment[1][5].RADDR7
address[7] => segment[1][4].WADDR7
address[7] => segment[1][4].RADDR7
address[7] => segment[1][3].WADDR7
address[7] => segment[1][3].RADDR7
address[7] => segment[1][2].WADDR7
address[7] => segment[1][2].RADDR7
address[7] => segment[1][1].WADDR7
address[7] => segment[1][1].RADDR7
address[7] => segment[1][0].WADDR7
address[7] => segment[1][0].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[1][7].WADDR8
address[8] => segment[1][7].RADDR8
address[8] => segment[1][6].WADDR8
address[8] => segment[1][6].RADDR8
address[8] => segment[1][5].WADDR8
address[8] => segment[1][5].RADDR8
address[8] => segment[1][4].WADDR8
address[8] => segment[1][4].RADDR8
address[8] => segment[1][3].WADDR8
address[8] => segment[1][3].RADDR8
address[8] => segment[1][2].WADDR8
address[8] => segment[1][2].RADDR8
address[8] => segment[1][1].WADDR8
address[8] => segment[1][1].RADDR8
address[8] => segment[1][0].WADDR8
address[8] => segment[1][0].RADDR8
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8
address[8] => segment[0][6].WADDR8
address[8] => segment[0][6].RADDR8
address[8] => segment[0][5].WADDR8
address[8] => segment[0][5].RADDR8
address[8] => segment[0][4].WADDR8
address[8] => segment[0][4].RADDR8
address[8] => segment[0][3].WADDR8
address[8] => segment[0][3].RADDR8
address[8] => segment[0][2].WADDR8
address[8] => segment[0][2].RADDR8
address[8] => segment[0][1].WADDR8
address[8] => segment[0][1].RADDR8
address[8] => segment[0][0].WADDR8
address[8] => segment[0][0].RADDR8
address[9] => segment[1][7].WADDR9
address[9] => segment[1][7].RADDR9
address[9] => segment[1][6].WADDR9
address[9] => segment[1][6].RADDR9
address[9] => segment[1][5].WADDR9
address[9] => segment[1][5].RADDR9
address[9] => segment[1][4].WADDR9
address[9] => segment[1][4].RADDR9
address[9] => segment[1][3].WADDR9
address[9] => segment[1][3].RADDR9
address[9] => segment[1][2].WADDR9
address[9] => segment[1][2].RADDR9
address[9] => segment[1][1].WADDR9
address[9] => segment[1][1].RADDR9
address[9] => segment[1][0].WADDR9
address[9] => segment[1][0].RADDR9
address[9] => segment[0][7].WADDR9
address[9] => segment[0][7].RADDR9
address[9] => segment[0][6].WADDR9
address[9] => segment[0][6].RADDR9
address[9] => segment[0][5].WADDR9
address[9] => segment[0][5].RADDR9
address[9] => segment[0][4].WADDR9
address[9] => segment[0][4].RADDR9
address[9] => segment[0][3].WADDR9
address[9] => segment[0][3].RADDR9
address[9] => segment[0][2].WADDR9
address[9] => segment[0][2].RADDR9
address[9] => segment[0][1].WADDR9
address[9] => segment[0][1].RADDR9
address[9] => segment[0][0].WADDR9
address[9] => segment[0][0].RADDR9
address[10] => segment[1][7].WADDR10
address[10] => segment[1][7].RADDR10
address[10] => segment[1][6].WADDR10
address[10] => segment[1][6].RADDR10
address[10] => segment[1][5].WADDR10
address[10] => segment[1][5].RADDR10
address[10] => segment[1][4].WADDR10
address[10] => segment[1][4].RADDR10
address[10] => segment[1][3].WADDR10
address[10] => segment[1][3].RADDR10
address[10] => segment[1][2].WADDR10
address[10] => segment[1][2].RADDR10
address[10] => segment[1][1].WADDR10
address[10] => segment[1][1].RADDR10
address[10] => segment[1][0].WADDR10
address[10] => segment[1][0].RADDR10
address[10] => segment[0][7].WADDR10
address[10] => segment[0][7].RADDR10
address[10] => segment[0][6].WADDR10
address[10] => segment[0][6].RADDR10
address[10] => segment[0][5].WADDR10
address[10] => segment[0][5].RADDR10
address[10] => segment[0][4].WADDR10
address[10] => segment[0][4].RADDR10
address[10] => segment[0][3].WADDR10
address[10] => segment[0][3].RADDR10
address[10] => segment[0][2].WADDR10
address[10] => segment[0][2].RADDR10
address[10] => segment[0][1].WADDR10
address[10] => segment[0][1].RADDR10
address[10] => segment[0][0].WADDR10
address[10] => segment[0][0].RADDR10
address[11] => lpm_decode:decoder.data[0]
address[11] => lpm_mux:mux.sel[0]
be => lpm_decode:decoder.enable
q[0] <= lpm_mux:mux.result[0]
q[1] <= lpm_mux:mux.result[1]
q[2] <= lpm_mux:mux.result[2]
q[3] <= lpm_mux:mux.result[3]
q[4] <= lpm_mux:mux.result[4]
q[5] <= lpm_mux:mux.result[5]
q[6] <= lpm_mux:mux.result[6]
q[7] <= lpm_mux:mux.result[7]


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_decode:decoder
data[0] => eq_node[0]~0.IN0
data[0] => eq_node[1].IN0
enable => eq_node[0].IN1
enable => eq_node[1].IN1
eq[0] <= altshift:external_latency_ffs.result[0]
eq[1] <= altshift:external_latency_ffs.result[1]


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_decode:decoder|altshift:external_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux
data[0][0] => muxlut:$00009.data[0]
data[0][1] => muxlut:$00011.data[0]
data[0][2] => muxlut:$00013.data[0]
data[0][3] => muxlut:$00015.data[0]
data[0][4] => muxlut:$00017.data[0]
data[0][5] => muxlut:$00019.data[0]
data[0][6] => muxlut:$00021.data[0]
data[0][7] => muxlut:$00023.data[0]
data[1][0] => muxlut:$00009.data[1]
data[1][1] => muxlut:$00011.data[1]
data[1][2] => muxlut:$00013.data[1]
data[1][3] => muxlut:$00015.data[1]
data[1][4] => muxlut:$00017.data[1]
data[1][5] => muxlut:$00019.data[1]
data[1][6] => muxlut:$00021.data[1]
data[1][7] => muxlut:$00023.data[1]
sel[0] => muxlut:$00023.select[0]
sel[0] => muxlut:$00021.select[0]
sel[0] => muxlut:$00019.select[0]
sel[0] => muxlut:$00017.select[0]
sel[0] => muxlut:$00015.select[0]
sel[0] => muxlut:$00013.select[0]
sel[0] => muxlut:$00011.select[0]
sel[0] => muxlut:$00009.select[0]
result[0] <= altshift:external_latency_ffs.result[0]
result[1] <= altshift:external_latency_ffs.result[1]
result[2] <= altshift:external_latency_ffs.result[2]
result[3] <= altshift:external_latency_ffs.result[3]
result[4] <= altshift:external_latency_ffs.result[4]
result[5] <= altshift:external_latency_ffs.result[5]
result[6] <= altshift:external_latency_ffs.result[6]
result[7] <= altshift:external_latency_ffs.result[7]


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|altshift:external_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00009
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00011
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00013
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00015
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00017
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00019
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00021
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


|tt_RAMx|lpm_ram_io1:inst1|lpm_ram_io:lpm_ram_io_component|altram:sram|lpm_mux:mux|muxlut:$00023
data[0] => result_node~0.IN1
data[1] => result_node~1.IN1
select[0] => altr_temp~0.IN0
select[0] => result_node~1.IN0
clock => clock_out.DATAIN
aclr => aclr_out.DATAIN
clken => clken_out.DATAIN
result <= result_node.DB_MAX_OUTPUT_PORT_TYPE
clock_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
aclr_out <= aclr.DB_MAX_OUTPUT_PORT_TYPE
clken_out <= clken.DB_MAX_OUTPUT_PORT_TYPE


