|computer
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|110.DATAA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|105~3.SDATA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|33.DATAB
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|110.DATAA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|105~3.SDATA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|61.DATAB
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|110.DATAA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|110.DATAA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|105~3.SDATA
DATA[7] => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|105~3.SDATA
DATA[7] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][7].DATAIN
DATA[7] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][7].DATAIN
DATA[7] => cpu:inst2|alu:inst2|74153:144|10~182.DATAD
DATA[7] => cpu:inst2|alu:inst2|74153:143|10~182.DATAD
DATA[6] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|28.DATAB
DATA[6] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|60.DATAB
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|102~1.DATAA
DATA[6] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][6].DATAIN
DATA[6] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][6].DATAIN
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|102~1.DATAA
DATA[6] => cpu:inst2|alu:inst2|74153:144|9~182.DATAD
DATA[6] => cpu:inst2|alu:inst2|74153:143|9~182.DATAD
DATA[5] => cpu:inst2|ir:inst3|45.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|24.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|59.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|87.DATAB
DATA[5] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][5].DATAIN
DATA[5] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][5].DATAIN
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|87.DATAB
DATA[5] => cpu:inst2|alu:inst2|74153:141|10~182.DATAD
DATA[5] => cpu:inst2|alu:inst2|74153:142|10~182.DATAD
DATA[4] => cpu:inst2|ir:inst3|44.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|23.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|58.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|9.DATAB
DATA[4] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][4].DATAIN
DATA[4] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][4].DATAIN
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|9.DATAB
DATA[4] => cpu:inst2|alu:inst2|74153:141|9~182.DATAD
DATA[4] => cpu:inst2|alu:inst2|74153:142|9~182.DATAD
DATA[3] => cpu:inst2|ir:inst3|35.DATAB
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|22.DATAB
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|57.DATAB
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|105~3.SDATA
DATA[3] => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|105~3.SDATA
DATA[3] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][3].DATAIN
DATA[3] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][3].DATAIN
DATA[3] => cpu:inst2|alu:inst2|74153:139|10~182.DATAD
DATA[3] => cpu:inst2|alu:inst2|74153:140|10~182.DATAD
DATA[2] => cpu:inst2|ir:inst3|34.DATAB
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|95~3.SDATA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|21.DATAB
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|95~3.SDATA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|56.DATAB
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|95~3.SDATA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|95~3.SDATA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|102~1.DATAA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|102~1.DATAA
DATA[2] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][2].DATAIN
DATA[2] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][2].DATAIN
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|102~1.DATAA
DATA[2] => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|102~1.DATAA
DATA[2] => cpu:inst2|alu:inst2|74153:139|9~182.DATAD
DATA[2] => cpu:inst2|alu:inst2|74153:140|9~182.DATAD
DATA[1] => cpu:inst2|ir:inst3|14.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|85~3.SDATA
DATA[1] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|20.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|85~3.SDATA
DATA[1] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|55.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|87.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|87.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|85~3.SDATA
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|85~3.SDATA
DATA[1] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][1].DATAIN
DATA[1] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][1].DATAIN
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|87.DATAB
DATA[1] => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|87.DATAB
DATA[1] => cpu:inst2|alu:inst2|74153:138|10~182.DATAD
DATA[1] => cpu:inst2|alu:inst2|74153:137|10~182.DATAD
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|81~3.SDATA
DATA[0] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|54.DATAB
DATA[0] => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|19.DATAB
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|81~3.SDATA
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|81~3.SDATA
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|81~3.SDATA
DATA[0] => cpu:inst2|ir:inst3|13.DATAB
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|9.DATAB
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|9.DATAB
DATA[0] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[1][0].DATAIN
DATA[0] => lpm_ram_io0:inst|lpm_ram_io:lpm_ram_io_component|altram:sram|segment[0][0].DATAIN
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|9.DATAB
DATA[0] => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|9.DATAB
DATA[0] => cpu:inst2|alu:inst2|74153:138|9~182.DATAD
DATA[0] => cpu:inst2|alu:inst2|74153:137|9~182.DATAD
CLOCK => cpu:inst2|alu:inst2|128.CLK
CLOCK => cpu:inst2|controller:inst|125.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|19.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|54.CLK
CLOCK => cpu:inst2|alu:inst2|126.CLK
CLOCK => cpu:inst2|alu:inst2|123.CLK
CLOCK => cpu:inst2|alu:inst2|122.CLK
CLOCK => cpu:inst2|alu:inst2|119.CLK
CLOCK => cpu:inst2|alu:inst2|118.CLK
CLOCK => cpu:inst2|alu:inst2|116.CLK
CLOCK => cpu:inst2|alu:inst2|114.CLK
CLOCK => cpu:inst2|alu:inst2|125.CLK
CLOCK => cpu:inst2|alu:inst2|127.CLK
CLOCK => cpu:inst2|alu:inst2|113.CLK
CLOCK => cpu:inst2|alu:inst2|115.CLK
CLOCK => cpu:inst2|alu:inst2|124.CLK
CLOCK => cpu:inst2|alu:inst2|121.CLK
CLOCK => cpu:inst2|alu:inst2|120.CLK
CLOCK => cpu:inst2|alu:inst2|117.CLK
CLOCK => cpu:inst2|ir:inst3|45.CLK
CLOCK => cpu:inst2|ir:inst3|44.CLK
CLOCK => cpu:inst2|ir:inst3|35.CLK
CLOCK => cpu:inst2|ir:inst3|34.CLK
CLOCK => cpu:inst2|ir:inst3|14.CLK
CLOCK => cpu:inst2|ir:inst3|13.CLK
CLOCK => cpu:inst2|controller:inst|126.CLK
CLOCK => cpu:inst2|controller:inst|37.CLK
CLOCK => cpu:inst2|controller:inst|38.CLK
CLOCK => cpu:inst2|controller:inst|39.CLK
CLOCK => cpu:inst2|controller:inst|40.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|110.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|33.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|28.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|24.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|23.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|22.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|21.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|20.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|110.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|61.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|60.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|59.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|58.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|57.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|56.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|55.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|81~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|81~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|81~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|81~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|95~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|85~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|95~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|85~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|110.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|110.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|95~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|95~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|85~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|85~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|105~3.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|87.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|9.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|99.CLK
CLOCK => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|99.CLK
/RESET => cpu:inst2|alu:inst2|128.ACLR
/RESET => cpu:inst2|controller:inst|125.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|19.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|54.ACLR
/RESET => cpu:inst2|alu:inst2|126.ACLR
/RESET => cpu:inst2|alu:inst2|123.ACLR
/RESET => cpu:inst2|alu:inst2|122.ACLR
/RESET => cpu:inst2|alu:inst2|119.ACLR
/RESET => cpu:inst2|alu:inst2|118.ACLR
/RESET => cpu:inst2|alu:inst2|116.ACLR
/RESET => cpu:inst2|alu:inst2|114.ACLR
/RESET => cpu:inst2|alu:inst2|125.ACLR
/RESET => cpu:inst2|alu:inst2|127.ACLR
/RESET => cpu:inst2|alu:inst2|113.ACLR
/RESET => cpu:inst2|alu:inst2|115.ACLR
/RESET => cpu:inst2|alu:inst2|124.ACLR
/RESET => cpu:inst2|alu:inst2|121.ACLR
/RESET => cpu:inst2|alu:inst2|120.ACLR
/RESET => cpu:inst2|alu:inst2|117.ACLR
/RESET => cpu:inst2|ir:inst3|45.ACLR
/RESET => cpu:inst2|ir:inst3|44.ACLR
/RESET => cpu:inst2|ir:inst3|35.ACLR
/RESET => cpu:inst2|ir:inst3|34.ACLR
/RESET => cpu:inst2|ir:inst3|14.ACLR
/RESET => cpu:inst2|ir:inst3|13.ACLR
/RESET => cpu:inst2|controller:inst|126.ACLR
/RESET => cpu:inst2|controller:inst|37.ACLR
/RESET => cpu:inst2|controller:inst|38.ACLR
/RESET => cpu:inst2|controller:inst|39.ACLR
/RESET => cpu:inst2|controller:inst|40.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|110.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|33.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|28.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|24.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|23.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|22.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|21.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|20.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|110.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|61.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|60.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|59.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|58.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|57.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|56.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|55.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|81~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|81~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|81~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|81~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|95~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|85~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|95~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|85~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|110.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|110.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|95~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|95~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:3|f74161:sub|85~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:171|f74161:sub|85~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|105~3.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:33|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:174|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|87.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|9.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:172|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:4|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:32|f74161:sub|99.ACLR
/RESET => cpu:inst2|pc_mar_ix:inst1|74161:173|f74161:sub|99.ACLR
N_FLG <= cpu:inst2|alu:inst2|128
DATA[7] <= DATA~3793
DATA[6] <= DATA~3794
DATA[5] <= DATA~3795
DATA[4] <= DATA~3796
DATA[3] <= DATA~3797
DATA[2] <= DATA~3798
DATA[1] <= DATA~3799
DATA[0] <= DATA~3800
Z_FLG <= cpu:inst2|alu:inst2|161~43
R_/W <= cpu:inst2|controller:inst|lpm_rom0:inst1|lpm_rom:lpm_rom_component|altrom:srom|lpm_mux:mux|muxlut:$00042|muxlut:$00016|result_node~5
ROM_Enable <= 32~100
ADDR[15] <= cpu:inst2|pc_mar_ix:inst1|MUX41:169|6~228
ADDR[14] <= cpu:inst2|pc_mar_ix:inst1|74283:136|f74283:sub|90~7
ADDR[13] <= cpu:inst2|pc_mar_ix:inst1|74283:136|f74283:sub|89~8
ADDR[12] <= cpu:inst2|pc_mar_ix:inst1|74283:136|f74283:sub|88~8
ADDR[11] <= cpu:inst2|pc_mar_ix:inst1|74283:135|f74283:sub|91~6
ADDR[10] <= cpu:inst2|pc_mar_ix:inst1|74283:135|f74283:sub|90~8
ADDR[9] <= cpu:inst2|pc_mar_ix:inst1|74283:135|f74283:sub|89~8
ADDR[8] <= cpu:inst2|pc_mar_ix:inst1|74283:135|f74283:sub|88~8
ADDR[7] <= cpu:inst2|pc_mar_ix:inst1|74283:133|f74283:sub|91~2
ADDR[6] <= cpu:inst2|pc_mar_ix:inst1|74283:133|f74283:sub|90~4
ADDR[5] <= cpu:inst2|pc_mar_ix:inst1|74283:133|f74283:sub|89~5
ADDR[4] <= cpu:inst2|pc_mar_ix:inst1|74283:133|f74283:sub|88~5
ADDR[3] <= cpu:inst2|pc_mar_ix:inst1|74283:131|f74283:sub|91~2
ADDR[2] <= cpu:inst2|pc_mar_ix:inst1|74283:131|f74283:sub|90~4
ADDR[1] <= cpu:inst2|pc_mar_ix:inst1|74283:131|f74283:sub|89~5
ADDR[0] <= cpu:inst2|pc_mar_ix:inst1|MUX41:155|6~15
RAM_Enable <= 37
RAM_WE <= inst5
RAM_OE <= inst4
A[7] <= cpu:inst2|alu:inst2|128
A[6] <= cpu:inst2|alu:inst2|126
A[5] <= cpu:inst2|alu:inst2|123
A[4] <= cpu:inst2|alu:inst2|122
A[3] <= cpu:inst2|alu:inst2|119
A[2] <= cpu:inst2|alu:inst2|118
A[1] <= cpu:inst2|alu:inst2|116
A[0] <= cpu:inst2|alu:inst2|114
ALU[7] <= cpu:inst2|alu:inst2|161mux:198|41~77
ALU[6] <= cpu:inst2|alu:inst2|161mux:199|41~817
ALU[5] <= cpu:inst2|alu:inst2|161mux:200|41~809
ALU[4] <= cpu:inst2|alu:inst2|161mux:201|41~809
ALU[3] <= cpu:inst2|alu:inst2|161mux:196|41~1309
ALU[2] <= cpu:inst2|alu:inst2|161mux:197|41~808
ALU[1] <= cpu:inst2|alu:inst2|161mux:195|41~809
ALU[0] <= cpu:inst2|alu:inst2|161mux:194|41~201
B[7] <= cpu:inst2|alu:inst2|127
B[6] <= cpu:inst2|alu:inst2|125
B[5] <= cpu:inst2|alu:inst2|124
B[4] <= cpu:inst2|alu:inst2|121
B[3] <= cpu:inst2|alu:inst2|120
B[2] <= cpu:inst2|alu:inst2|117
B[1] <= cpu:inst2|alu:inst2|115
B[0] <= cpu:inst2|alu:inst2|113
IR[5] <= cpu:inst2|ir:inst3|45
IR[4] <= cpu:inst2|ir:inst3|44
IR[3] <= cpu:inst2|ir:inst3|35
IR[2] <= cpu:inst2|ir:inst3|34
IR[1] <= cpu:inst2|ir:inst3|14
IR[0] <= cpu:inst2|ir:inst3|13
MSC[3] <= cpu:inst2|controller:inst|lpm_rom0:inst1|lpm_rom:lpm_rom_component|altrom:srom|lpm_mux:mux|muxlut:$00052|muxlut:$00016|result_node~5
MSC[2] <= cpu:inst2|controller:inst|lpm_rom0:inst1|lpm_rom:lpm_rom_component|altrom:srom|lpm_mux:mux|muxlut:$00050|muxlut:$00016|result_node~5
MSC[1] <= cpu:inst2|controller:inst|lpm_rom0:inst1|lpm_rom:lpm_rom_component|altrom:srom|lpm_mux:mux|muxlut:$00048|muxlut:$00016|result_node~5
MSC[0] <= cpu:inst2|controller:inst|lpm_rom0:inst1|lpm_rom:lpm_rom_component|altrom:srom|lpm_mux:mux|muxlut:$00046|muxlut:$00016|result_node~5
STATE[5] <= cpu:inst2|controller:inst|125
STATE[4] <= cpu:inst2|controller:inst|126
STATE[3] <= cpu:inst2|controller:inst|37
STATE[2] <= cpu:inst2|controller:inst|38
STATE[1] <= cpu:inst2|controller:inst|39
STATE[0] <= cpu:inst2|controller:inst|40
X[15] <= cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|110
X[14] <= cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|95~2
X[13] <= cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|87
X[12] <= cpu:inst2|pc_mar_ix:inst1|74161:126|f74161:sub|9
X[11] <= cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|105~3
X[10] <= cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|95~3
X[9] <= cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|87
X[8] <= cpu:inst2|pc_mar_ix:inst1|74161:125|f74161:sub|9
X[7] <= cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|105~3
X[6] <= cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|95~3
X[5] <= cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|87
X[4] <= cpu:inst2|pc_mar_ix:inst1|74161:124|f74161:sub|9
X[3] <= cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|105~3
X[2] <= cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|95~3
X[1] <= cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|85~3
X[0] <= cpu:inst2|pc_mar_ix:inst1|74161:123|f74161:sub|81~3
XDISP[7] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|33
XDISP[6] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|28
XDISP[5] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|24
XDISP[4] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|23
XDISP[3] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|22
XDISP[2] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|21
XDISP[1] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|20
XDISP[0] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|19
Y[15] <= cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|110
Y[14] <= cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|95~2
Y[13] <= cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|87
Y[12] <= cpu:inst2|pc_mar_ix:inst1|74161:130|f74161:sub|9
Y[11] <= cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|105~3
Y[10] <= cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|95~3
Y[9] <= cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|87
Y[8] <= cpu:inst2|pc_mar_ix:inst1|74161:129|f74161:sub|9
Y[7] <= cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|105~3
Y[6] <= cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|95~3
Y[5] <= cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|87
Y[4] <= cpu:inst2|pc_mar_ix:inst1|74161:128|f74161:sub|9
Y[3] <= cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|105~3
Y[2] <= cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|95~3
Y[1] <= cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|85~3
Y[0] <= cpu:inst2|pc_mar_ix:inst1|74161:127|f74161:sub|81~3
YDISP[7] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|61
YDISP[6] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|60
YDISP[5] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|59
YDISP[4] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|58
YDISP[3] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|57
YDISP[2] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|56
YDISP[1] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|55
YDISP[0] <= cpu:inst2|pc_mar_ix:inst1|xdr_ydr:inst|54

