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Sample behavioral waveforms for design file altsyncram0.vhd

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altsyncram0.vhd . For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0, 1, 0, 0, 0, ...). The design altsyncram0.vhd has one read/write port. The read/write port has 4096 words of 8 bits each. The ram block type of the design is . The output of the read/write port is unregistered.

Fig. 1 : Wave showing read operation.

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock.

Fig. 2 : Waveform showing write operation

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. During a write cycle, the new data flows through to the output.