Product Families > Programmable Logic > CPLDs > CY37128 CY37128 UltraLogic™ 128-Macrocell ISR™ CPLD Preliminary Features 128 macrocells in eight logic blocks In-System Reprogrammable (ISR™) JTAG-compliant on-board programming Design changes don’t cause pinout changes Design changes don’t cause timing changes Up to 128 I/Os Plus 5 dedicated inputs including 4 clock inputs High speed fMAX = 167 MHz tPD = 6.5 ns tS = 4.0 ns tCO = 4.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis 5V and 3.3V I/O capability User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant 84-160 pins in TQFP, PLCC, and CLCC packages Pinout compatible with the CY37064/37064V, CY37128V, CY37192/37192V, CY37256/37256V, CY7C373i, CY7C374i, CY7C375i July 15, 1999 To download full device info in Adobe Acrobat: [ Adobe Acrobat(PDF)(277K) ]

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