Class Examples
Topic Examples
NAND in VHDL
  • NAnd2bit.vhd
  • NAnd2.vhd
    • Behavioral example
  • mux41.vhd
    • Mixed-logic in VHDL
    (with report file)
  • mix_log.vhd
  • Report file operators
  • mix_log.fit.eqn from Quartus 8.0 sp1
  • mix_log.rpt from Quartus 4.0
    • Octal 2-input
    MUX examples
  • mux2to1a.vhd
  • mux2to1b.vhd
  • mux2to1c.vhd
  • mux2to1d.vhd
  • mux2to1e.vhd
  • mux2to1f.vhd
    • Octal 4-input
    MUX examples
  • mux4to1a.vhd
  • mux4to1b.vhd
  • mux4to1c.vhd
    • Structural VHDL
  • dreginst.vhd
  • AAnd2.vhd
  • OOrd2.vhd
  • And3_Or3.vhd
    • Comparators in VHDL
  • compare_1.vhd
  • compare_2.vhd
  • compare_3.vhd
  • compare_4.vhd (using a process)
  • compare_5.vhd (using when-else)
  • compare_6.vhd (using structural VHDL)
  • aand4.vhd
  • xxnor2.vhd
    • Example Spec Sheet
  • aand2.pdf
    • LCELL Use
  • LCELL_And3_Or3.vhd (Use the aand.vhd and oord2.vhd files above.)
    • Processes,
    Inadvertant Latches,
    Intermediate Signals
  • mux4to1a.vhd
  • mux4to1b.vhd
  • mux4to1c.vhd
  • muxlatb.vhd (BAD process!!!)
  • muxlat1.vhd (Good process)
  • muxlat2.vhd (Using a variable)
  • fulladd.vhd (Using line numbers)
  • fulladd_2.vhd (Using LCELL to keep intermediate signals)
  • fulladd_3.vhd (Using LCELL for intermediate outputs)
    • Registers and Latches
  • inadvert_latch.vhd
  • dregbeh.vhd
  • dlatbeh.vhd
  • t_reg8.vhd
  • dregares.vhd
  • dregaset.vhd
  • dregsysr.vhd
  • dreginst.vhd
    • More
    MUX example
  • mux_with.vhd
  • mux_case.vhd
    • Product Term
    Expansion
  • Product Term Expansion Files (VHDL for PALs from Warp, not Quartus)
    • Counters
  • Counters
    • Shifters
  • Shifters
    • Tri-state &
    Don't Cares
  • Tri-state & Don't Cares
    • Ranges & Radix
  • range1.vhd
  • radix.vhd
    • Process Waiting
  • wait_unt.vhd
  • wait_on.vhd
  • jk_no_wait.vhd
    • Moore Machines
  • moore_1.vhd
  • moore_2.vhd
  • moore_3.vhd
  • moore_b.vhd
  • moore_oh.vhd
  • moore_o.vhd
    • Answering Machine
    (State Machine
    Examples)
  • mealy_1.vhd
  • ansmach1.vhd
  • ansmach2.vhd
  • ansmach3.vhd
  • ansmach4.vhd
  • ansmach5.vhd
  • ansmach6.vhd
  • ansmach7.vhd
  • delayed.vhd
    • Generate
  • generate_1.vhd
  • parity8.vhd (uses a CONSTANT)
  • parity8a.vhd (uses a GENERIC)
  • tri_stat.vhd
  • xor2.vhd
    • Bus Examples
  • bus.bdf (not VHDL)
  • bus_bi.bdf (not VHDL)
  • bus_bi_2.bdf (not VHDL)
  • bus_bi_vhd.vhd (VHDL)
    • Attributes,Types,Ranges,Tables
  • attributes.vhd
  • attributes.vwf Functional simulation using "Design Entry (all names)"
  • range1.vhd
  • table.vhd
  • table0.vhd
  • table1.vhd
  • table2.vhd
  • table3.vhd