library ieee;
use ieee.std_logic_1164.all;
entity MOORE_EX2 is port(
	Clk, Reset:	in std_logic;
	Req, PWait:	in std_logic;
	Retry_Out, Ack_Out:	out std_logic);
end MOORE_EX2;

architecture behavior of MOORE_EX2 is
	type FSM_States is (Idle, Retry, Ack);
	signal Wait_Gen:	FSM_States;
begin
	MOORE_2: process (Clk, Reset) begin
		if Reset='1' then 
			Wait_Gen <= Idle; Retry_Out <= '0'; Ack_Out <= '0';
		elsif (Clk'event and Clk='1') then
			Retry_Out <= '0'; -- a default; coud do Ack_Out too
			case Wait_Gen is
				when Idle =>	if Req='0'
				   then Wait_Gen<=Retry; Retry_Out<='1';	Ack_Out<='0';
				   else Wait_Gen<=Idle;                  Ack_Out<='0'; end if;
				when Retry =>if PWait='1'
				   then Wait_Gen<=Ack; 		Ack_Out<='1';
				   else Wait_Gen<=Retry; Retry_Out<='1'; Ack_Out<='0'; end if;
				when Ack =>	Wait_Gen<=Idle;		Ack_Out<='0';
				when others =>	Wait_Gen<=Idle;		Ack_Out<='0';
-- Must define what happens to Ack_Out in others (above) or a latch is
-- made to maintain its present state.
			end case;
		end if;
	end process MOORE_2;
end behavior;