-- Fuction of adder and multiplier
entity FS is port(
		FSEL : in BIT;
		A,B    : in BIT_VECTOR(2 downto 0);
		FOUT : out BIT_VECTOR(5 downto 0) );
end FS;

architecture STRUCTURE of FS is
component AND2 port(
	A,B : in BIT;
	C :	 out BIT);
end component;

component MUX2_6 port(
	SEL: in BIT;
	D0,D1: in BIT_VECTOR(5 downto 0);
	Z: out BIT_VECTOR(5 downto 0) );
end component;

component HA port(
	A,B    : in BIT;
	FOUT,COUT : out BIT);
end component;

component FA port(
	CIN,A,B  : in BIT;
	FOUT,COUT : out BIT);
end component;

SIGNAL a1b0, a2b0, a0b1, a1b1, a2b1, a0b2, a1b2, a2b2 : BIT;
SIGNAL cu10,su11,cu11,cu12,su13,cu13,cu14,cu16,cu17   : BIT;
SIGNAL p : BIT_VECTOR(5 downto 0);
SIGNAL s : BIT_VECTOR(5 downto 0);
begin
-- multiplier
U1  : AND2 port map(A(0),B(0),p(0));
U2  : AND2 port map(A(1),B(0),a1b0);
U3  : AND2 port map(A(2),B(0),a2b0);
U4  : AND2 port map(A(0),B(1),a0b1);
U5  : AND2 port map(A(1),B(1),a1b1);
U6  : AND2 port map(A(2),B(1),a2b1);
U7  : AND2 port map(A(0),B(2),a0b2);
U8  : AND2 port map(A(1),B(2),a1b2);
U9  : AND2 port map(A(2),B(2),a2b2);
U10 : HA port map(a1b0,a0b1,p(1),cu10);
U11 : HA port map(a2b0,a1b1, su11, cu11);
U12 : FA port map(cu10,a0b2,su11,p(2),cu12);
U13 : FA port map(cu11,a2b1,a1b2,su13,cu13);
U14 : HA port map(cu12,su13,p(3),cu14);
U15 : FA port map(cu14,a2b2,cu13,p(4),p(5));
-- adder
U16 : HA port map(A(0),B(0),s(0),cu16);
U17 : FA port map(cu16,A(1),B(1),s(1),cu17);
U18 : FA port map(cu17,A(2),B(2),s(2),s(3));
	s(5 downto 4) <= '0' & '0'; --most significant bits of add=0
U19 : MUX2_6 port map(FSEL,p,s,FOUT);
end STRUCTURE;