library ieee;
use ieee.std_logic_1164.all;
entity DFF_EN_WAIT is port(
		D:			in std_logic;
		Enable,Clk: in std_logic;
		Q:			out std_logic);
end DFF_EN_WAIT;
architecture behavior of DFF_EN_WAIT is
begin
	WAIT_PROC: process begin
		wait until Clk='1'; 
		if (Enable = '1') then
			Q <= D;
		else
			Q <= '0';
		end if; 
	end process WAIT_PROC;
end behavior;