-- Arithmetic shift right example (sra)
library ieee;
use ieee.std_logic_1164.all;
-- Use Warp's below package so can do math with std_logic_vector's
use work.std_arith.all; 
-- ****************************************************

PACKAGE My_Package IS

-- ***********************************
-- Component Declaration
-- 2-input AND gate
component AND2 port(
	A:	in std_logic;
	B:	in std_logic;
	X:	out std_logic);
end component;
-- ***********************************
-- Component Declaration 
-- 2-input OR gate
component OR2 port(
	A,B:	in std_logic;
	Z:		out std_logic);
end component;
-- ***********************************
function shift_right(signal Q: in std_logic_vector(7 downto 0);
					 signal ShiftIn: in std_logic) return std_logic_vector;

end package My_Package;
-- ****************************************************

library ieee;
use ieee.std_logic_1164.all;
-- Use Warp's below package so can do math with std_logic_vector's
use work.std_arith.all; 

entity AND2 is port(
	A,B:	in std_logic;
	X: 	out std_logic);
end AND2;

architecture archAnd2 of AND2 is
begin
	X <= A and B;
end archAnd2;
-- ****************************************************

library ieee;
use ieee.std_logic_1164.all;
-- Use Warp's below package so can do math with std_logic_vector's
use work.std_arith.all; 
entity OR2 is port(
	A,B:	in std_logic;
	Z: 	out std_logic);
end OR2;

architecture archor2 of OR2 is
begin
	Z <= A or B;
end archor2;
-- ****************************************************

PACKAGE BODY My_Package IS

function shift_right(signal Q: in std_logic_vector(7 downto 0);
					 signal ShiftIn: in std_logic) return std_logic_vector is
	variable x:  std_logic_vector(7 downto 0);
	begin	
	  x := Q srl 1;
	  x(7) := ShiftIn;
 	  return x;
end function;

end package body My_Package;