library ieee;
use ieee.std_logic_1164.all;
entity PROD_EXP is
	port(
		A: in std_logic_vector(19 downto 0);
		C: buffer std_logic;
		D: out std_logic);
end PROD_EXP;

architecture behavior of PROD_EXP is

begin
	PROD_EXP_process: process (A)
	variable CC: std_logic;
	begin
		CC := '0';
		for i in 15 downto 0 loop
			CC := (A(i) AND A(i+1)) OR CC;
		end loop;
		C <= CC;
	end process;		
		
	D <= C OR (A(16) AND A(17));
end behavior;