library ieee;
use ieee.std_logic_1164.all;
entity TT is
	port(
		A,B,Sel: in std_logic;
		X,Y: out std_logic);
end TT;

architecture behavior of TT is
signal C: std_logic;
begin
	X <= A or B when (Sel='1') else 'Z';
	Y <= A and B when (Sel='0') else 'Z';
end behavior;