library ieee;
use ieee.std_logic_1164.all;
entity TRI_STATE is port(
	X:	in std_logic;
	OE:	in std_logic;
	Y:	out std_logic);
end TRI_STATE;

architecture behavior of TRI_STATE is
begin
--	TRI: process (OE, X) begin
--		if OE='1' then Y <= X; else Y <= 'Z'; end if;
--	end process TRI;
	Y <= X	when OE ='1' else 'Z';
end behavior;