library ieee;
use ieee.std_logic_1164.all;
entity MOORE_EXA is port(
	Clk, Reset:	in std_logic;
	Req, PWait:	in std_logic;
	Retry_Out, Ack_Out:	out std_logic);
end MOORE_EXA;

architecture behavior of MOORE_EXA is
	type FSM_States is (Retry, Idle, Ack);
attribute enum_encoding of FSM_States: type is "11 00 01";
	signal Wait_Gen:	FSM_States;
begin
	MOORE_A: process (Clk, Reset) begin
		if Reset='1' then Wait_Gen<=Idle; --asynch reset
		elsif (Clk'event and Clk='1') then
			case Wait_Gen is
				when Idle =>	if Req='0'	then Wait_Gen<=Retry;
							else Wait_Gen<=Idle;
						end if;
				when Retry =>	if PWait='1'	then Wait_Gen<=Ack;
							else Wait_Gen<=Retry;
						end if;
				when Ack =>	Wait_Gen<=Idle;
				when others =>	Wait_Gen<=Idle;
			end case;
		end if;
	end process MOORE_A;
	Retry_Out <= '1' when (Wait_Gen=Retry) else '0';
	Ack_Out   <= '1' when (Wait_Gen=Ack) else '0';
end behavior;