library ieee;
use ieee.std_logic_1164.all;
entity PROD_EXP is
	port(
		A: in std_logic_vector(19 downto 0);
--XX		C: buffer std_logic;
		D: out std_logic);
end PROD_EXP;

architecture behavior of PROD_EXP is
signal C: std_logic;
begin
	C <= (A(0) AND A(1))   OR (A(1) AND A(2))   OR (A(2) AND A(3))   OR 
		 (A(3) AND A(4))   OR (A(4) AND A(5))   OR (A(5) AND A(6))   OR 
		 (A(6) AND A(7))   OR (A(7) AND A(8))   OR (A(8) AND A(9))   OR 
		 (A(9) AND A(10))  OR (A(10) AND A(11)) OR (A(11) AND A(12)) OR 
		 (A(12) AND A(13)) OR (A(13) AND A(14)) OR (A(14) AND A(15)) OR 
		 (A(15) AND A(16)) ;

	D <= C OR (A(16) AND A(17));
end behavior;