library ieee;
use ieee.std_logic_1164.all;

entity TT is port(
	A,B:	in std_logic;
	Q:		buffer std_logic_vector(7 downto 0)
);
end TT;

architecture behavior of TT is
begin
	Q(7 downto 4) <= (others=>'0');
	Q(3 downto 2) <= A & B; --concatenate
	Q(1 downto 0) <= (A,B); --aggregate
	--Q(0 to 1) <= A & B; --does not work
end behavior;