library ieee;
library TestLib;
use ieee.std_logic_1164.all;
use TestLib.my_package.all;
entity AND3_OR3 is port(
	A,B,C:	in std_logic;
	Y,Z: 	out std_logic);
end AND3_OR3;

architecture structure of AND3_OR3 is 
-- Word "structure" above can be anything; just repeat it at
-- the end of this architecture
signal T1,T2: std_logic;

-- ***********************************
begin
	U1: AND2 port map(A,B,T1);
	U2: AND2 port map(T1,C,Y);
	U3: OR2 port map(A,B,T2);
	U4: OR2 port map(T2,C,Z);
end structure;