library ieee; 
use ieee.std_logic_1164.all;
use work.std_arith.all; --need for std_match

entity TEST_LOOK_UP is
	port (
	A: in std_logic_vector(2 downto 0);
	B: out std_logic_vector(1 downto 0)
);
end TEST_LOOK_UP;
7
architecture behavior of TEST_LOOK_UP is 
	type Table is array(0 to 7) of std_logic_vector(4 downto 0);
	constant MyTable: Table := (
--		3 inputs / 2 outputs
             "00011",   
             "00110",
             "01001", 
             "01100",
             "10011",   
             "10110",
             "11001", 
             "11101"
	        );
	 begin
		process(A)
		variable X:	std_logic_vector(4 downto 0);
		begin
			for Count in 0 to 7 loop
				X := MyTable(Count);
				if std_match(A,X(4 downto 2)) then
					B <= X(1 downto 0);
				end if;
			end loop;       
		end process;
end behavior;