library ieee;
use ieee.std_logic_1164.all;
entity JK_Latch is port(
		J,K:	in std_logic;
		Q: 	buffer std_logic);
end JK_Latch;
architecture behavior of JK_Latch is
begin
	JK_Lat: process begin
		if 	(J='0' and K='0') then Q <= Q;
		elsif	(J='0' and K='1') then Q <= '0';
		elsif	(J='1' and K='0') then Q <= '1';
		else	Q <= not(Q);
		end if;
		wait on J,K,Q;
	end process JK_Lat;
end behavior;