library ieee;
use ieee.std_logic_1164.all;

entity ATTRIBUTES is port(
	Clk, Reset:	in std_logic;
	Q: 	out std_logic_vector(2 downto 0);
	TC:		out std_logic
);
end ATTRIBUTES ;

architecture behavior of ATTRIBUTES is
	constant ss0: std_logic_vector(2 downto 0) := "000";
	constant ss1: std_logic_vector(2 downto 0) := "001";
	constant ss2: std_logic_vector(2 downto 0) := "010";
	constant ss3: std_logic_vector(2 downto 0) := "011";
	constant ss4: std_logic_vector(2 downto 0) := "100";
	constant ss5: std_logic_vector(2 downto 0) := "101";
	constant ss6: std_logic_vector(2 downto 0) := "110";
	constant ss7: std_logic_vector(2 downto 0) := "111";
	type States is (S0,S1,S2,S3,S4,S5,S6,S7);
	signal Cnt: States;
begin
	CNT_UP: process(Reset,Clk) begin
	if (Reset='1') then 
		TC <= '0'; Cnt <= States'left; Q <= ss0;
	elsif RISING_EDGE(Clk) then
		TC <= '0';
		case Cnt is
			when S0 => Cnt <= S1; Q <= ss1;
			when S1 => Cnt <= S2; Q <= ss2;
			when S2 => Cnt <= S3; Q <= ss3;
			when S3 => Cnt <= S4; Q <= ss4;
			when S4 => Cnt <= S5; Q <= ss5;
			when S5 => Cnt <= S6; Q <= ss6;
			when S6 => Cnt <= States'right;  Q <= ss7; TC <= '1';
			when S7 => Cnt <= States'left;  Q <= ss0;
			when others => Cnt <= S0; Q <= ss0;
 		end case;
	end if;
	end process CNT_UP;
end behavior;