library ieee;
use ieee.std_logic_1164.all;
entity COMPARE_2 is port(
	A,B:	in	std_logic_vector(3 downto 0);
	AEqB:	out	std_logic);
end COMPARE_2;
architecture behavior of COMPARE_2 is
begin
	AEqB <= not(
		( A(0) xor B(0) ) or ( A(1) xor B(1) ) or
		( A(2) xor B(2) ) or
		( A(3) xor B(3) )  );
end behavior;