library ieee;
use ieee.std_logic_1164.all;
entity COMPARE_3 is port(
	A,B:	in	std_logic_vector(3 downto 0);
	AEqB:	out	std_logic);
end COMPARE_3;
architecture behavior of COMPARE_3 is
begin
	AEqB <=	not( A(0) xor B(0) ) and
			not( A(1) xor B(1) ) and
			not( A(2) xor B(2) ) and
			not( A(3) xor B(3) );
end behavior;