library ieee;
use ieee.std_logic_1164.all;
entity COMPARE_4 is port(
	A,B:	in	std_logic_vector(3 downto 0);
	AEqB:	out	std_logic);
end COMPARE_4 ;

architecture behavior of COMPARE_4 is
begin
	COMP4: process(A,B) begin
		if A=B then
			AEQB <= '1';
		else
			AEQB <= '0';
		end if;
	end process COMP4;
end behavior;