-- Counter with a Synchronous Clear

library ieee;
use ieee.std_logic_1164.all;

entity CNTUP2 is port(
	Clk,SynchClr:	in std_logic;
	TC:				out std_logic;
	Q:				buffer std_logic_vector(3 downto 0)
);
end CNTUP2;

architecture behavior of CNTUP2 is
	constant s0: std_logic_vector(3 downto 0) := "0000";
	constant s1: std_logic_vector(3 downto 0) := "0001";
	constant s2: std_logic_vector(3 downto 0) := "0010";
	constant s3: std_logic_vector(3 downto 0) := "0011";
	constant s4: std_logic_vector(3 downto 0) := "0100";
	constant s5: std_logic_vector(3 downto 0) := "0101";
	constant s6: std_logic_vector(3 downto 0) := "0110";
	constant s7: std_logic_vector(3 downto 0) := "0111";
	constant s8: std_logic_vector(3 downto 0) := "1000";
	constant s9: std_logic_vector(3 downto 0) := "1001";
	constant s10: std_logic_vector(3 downto 0) := "1010";
	constant s11: std_logic_vector(3 downto 0) := "1011";
	constant s12: std_logic_vector(3 downto 0) := "1100";
	constant s13: std_logic_vector(3 downto 0) := "1101";
	constant s14: std_logic_vector(3 downto 0) := "1110";
	constant s15: std_logic_vector(3 downto 0) := "1111";
begin
	CNT_UP: process(Clk) begin
		if RISING_EDGE(Clk) then
			TC <= '0';
			case Q is
				when S0 => Q <= S1;
				when S1 => Q <= S2;
				when S2 => Q <= S3;
				when S3 => Q <= S4;
				when S4 => Q <= S5;
				when S5 => Q <= S6;
				when S6 => Q <= S7;
				when S7 => Q <= S8;
				when S8 => Q <= S9;
				when S9 => Q <= S10;
				when S10 => Q <= S11;
				when S11 => Q <= S12;
				when S12 => Q <= S13;
				when S13 => Q <= S14;
				when S14 => Q <= S15;  TC <= '1';
				when S15 => Q <= S0;
				when others => Q <= S0;
 			end case;
			if SynchClr='1' then Q <= "0000"; TC <= '0'; end if;
		end if;
	end process CNT_UP;
end behavior;