library ieee;
use ieee.std_logic_1164.all;

entity DELAYED is
	port (
		clk:		in std_logic;
		state:		buffer std_logic_vector(3 downto 0);
		even:		out std_logic;
		odd:		out std_logic;
		prime:		out std_logic;
		even_d:		out std_logic;
		odd_d:		out std_logic;
		prime_d:	out std_logic
	);
end DELAYED;

architecture behavior of DELAYED is
	constant s00: std_logic_vector(3 downto 0) := "0000";
	constant s01: std_logic_vector(3 downto 0) := "0001";
	constant s02: std_logic_vector(3 downto 0) := "0010";
	constant s03: std_logic_vector(3 downto 0) := "0011";
	constant s04: std_logic_vector(3 downto 0) := "0100";
	constant s05: std_logic_vector(3 downto 0) := "0101";
	constant s06: std_logic_vector(3 downto 0) := "0110";
	constant s07: std_logic_vector(3 downto 0) := "0111";
	constant s08: std_logic_vector(3 downto 0) := "1000";
	constant s09: std_logic_vector(3 downto 0) := "1001";
	constant s10: std_logic_vector(3 downto 0) := "1010";
	constant s11: std_logic_vector(3 downto 0) := "1011";
	constant s12: std_logic_vector(3 downto 0) := "1100";
	constant s13: std_logic_vector(3 downto 0) := "1101";
	constant s14: std_logic_vector(3 downto 0) := "1110";
	constant s15: std_logic_vector(3 downto 0) := "1111";
	signal even_d_dan: std_logic;
begin
	DELAYED_STATE: process (clk)
		begin
			if (clk'event and clk='1') then
				case state is
					when s00 =>
						state <= s01;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s01 => 
						state <= s02;
						even_d <= '0'; odd_d <= '1'; prime_d <= '0';
					when s02 => 
						state <= s03;
						even_d <= '1'; odd_d <= '0'; prime_d <= '1';
					when s03 => 
						state <= s04;
						even_d <= '0'; odd_d <= '1'; prime_d <= '1';
					when s04 => 
						state <= s05;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s05 => 
						state <= s06;
						even_d <= '0'; odd_d <= '1'; prime_d <= '1';
					when s06 => 
						state <= s07;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s07 => 
						state <= s08;
						even_d <= '0'; odd_d <= '1'; prime_d <= '1';
					when s08 => 
						state <= s09;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s09 => 
						state <= s10;
						even_d <= '0'; odd_d <= '1'; prime_d <= '0';
					when s10 => 
						state <= s11;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s11 => 
						state <= s12;
						even_d <= '0'; odd_d <= '1'; prime_d <= '1';
					when s12 => 
						state <= s13;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s13 => 
						state <= s14;
						even_d <= '0'; odd_d <= '1'; prime_d <= '1';
					when s14 => 
						state <= s15;
						even_d <= '1'; odd_d <= '0'; prime_d <= '0';
					when s15 => 
						state <= s00;
						even_d <= '0'; odd_d <= '1'; prime_d <= '0';
					when others =>
						state <= s00;
						even_d <= '0'; odd_d <= '0'; prime_d <= '0';
				end case;
			end if;
		end process DELAYED_STATE;

	NONDELAYED_OUTPUTS: process (state)
		begin
			case state is
				when s00 =>
					even <= '1'; odd <= '0'; prime <= '0';
				when s01 => 
					even <= '0'; odd <= '1'; prime <= '0';
				when s02 => 
					even <= '1'; odd <= '0'; prime <= '1';
				when s03 => 
					even <= '0'; odd <= '1'; prime <= '1';
				when s04 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s05 => 
					even <= '0'; odd <= '1'; prime <= '1';
				when s06 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s07 => 
					even <= '0'; odd <= '1'; prime <= '1';
				when s08 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s09 => 
					even <= '0'; odd <= '1'; prime <= '0';
				when s10 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s11 => 
					even <= '0'; odd <= '1'; prime <= '1';
				when s12 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s13 => 
					even <= '0'; odd <= '1'; prime <= '1';
				when s14 => 
					even <= '1'; odd <= '0'; prime <= '0';
				when s15 => 
					even <= '0'; odd <= '1'; prime <= '0';
				when others => 
					even <= '0'; odd <= '0'; prime <= '0';
			end case;
		end process NONDELAYED_OUTPUTS;
end behavior;