library ieee;
use ieee.std_logic_1164.all;
entity GENER_1 is port(
	Ins:		in std_logic_vector(7 downto 0);
	OE:			in std_logic;
	Outs: 	out std_logic_vector(7 downto 0));
end GENER_1 ;

architecture structure of GENER_1 is 
component TRI_STAT port(
	X:	in std_logic;
	OE:	in std_logic;
	Y:	out std_logic);
end component;
-- ***********************************
begin
	Make_TriState:
	for I in 0 to 7 generate
		u0to7: TRI_STAT port map (Ins(I), OE, Outs(I));
	end generate;
end structure;