library ieee;
use ieee.std_logic_1164.all;
entity MOORE_3 is port(
	Clk, Reset:	in std_logic;
	Req, PWait:	in std_logic;
	Retry_Out, Ack_Out:	out std_logic);
end MOORE_3;

architecture behavior of MOORE_3 is
	signal Wait_Gen:	std_logic_vector(1 downto 0);
	constant Idle:	std_logic_vector(1 downto 0) := "00";
	constant Retry:	std_logic_vector(1 downto 0) := "01";
	constant Ack:	std_logic_vector(1 downto 0) := "10";
-- Note that Retry and Ack have reversed state bit assignments
-- from what Quartus did in the first two examples
begin
	MOORE3: process (Clk, Reset) begin
		if Reset='1' then Wait_Gen<=Idle; --asynch reset
		elsif (Clk'event and Clk='1') then
			case Wait_Gen is
				when Idle =>	if Req='0'	then Wait_Gen<=Retry;
							else Wait_Gen<=Idle;
						end if;
				when Retry =>	if PWait='1'	then Wait_Gen<=Ack;
							else Wait_Gen<=Retry;
						end if;
				when Ack =>	Wait_Gen<=Idle;
				when others =>	Wait_Gen<=Idle;
			end case;
		end if;
	end process MOORE3;
	Retry_Out <= Wait_Gen(0);
	Ack_Out   <= Wait_Gen(1);
end behavior;