library ieee;
use ieee.std_logic_1164.all;

entity RANGE1 is port(
	A,B:	in std_logic;
	Q:		buffer std_logic_vector(7 downto 0)
);
end RANGE1 ;

architecture behavior of RANGE1 is
begin
--	Q(7 downto 4) <= (others=>'0'); -- Works fine in Quartus

	Q(7 downto 4) <= A & A & "00"; 
--	Warning about Q5 and Q4 stuck at GND

	Q(3 downto 2) <= A & B; --concatenate

	Q(1 downto 0) <= (A,B); --aggregate

--	Q(0 to 1) <= A & B; --Quartus gives an Error
--	Error: VHDL error at range1.vhd ... direction of object slice
--  must be the same as range of direction of object

end behavior;