library ieee; 
use ieee.std_logic_1164.all;

entity TABLE is
	port (
	A: in std_logic_vector(1 downto 0);
	B: out std_logic_vector(1 downto 0)
);
end TABLE ;

architecture behavior of TABLE is 
--	subtype MyData is std_logic_vector(3 downto 0);
	TYPE Table is array(0 to 3) of std_logic_vector(3 downto 0);
--	Below does NOT work in MP2, but does in other VHDL's
	CONSTANT MyTable: Table := (
--		2 inputs (A1:A0) / 2 outputs (B1:B0)
             "0000",   
             "0111",
             "1001", 
             "1110"
	        );
	 begin
		process(A)
		variable X:	std_logic_vector(3 downto 0);
--		variable X: my_data;
		begin
			for count in 0 to 3 loop
				X := MyTable(count);
				if (A=X(3 downto 2)) then
					B <= X(1 downto 0);
				end if;
			end loop;       
		end process;
end behavior;