library ieee; 
use ieee.std_logic_1164.all;

entity TABLE2 is
	port (
	A: in std_logic_vector(2 downto 0);
	B: out std_logic_vector(1 downto 0)
);
end TABLE2 ;

architecture behavior of TABLE2 is 
	constant	Rows: integer :=8;
	constant	Cols: integer :=5;
	subtype MyData is std_logic_vector(Cols-1 downto 0);
	type Table is array(0 to Rows-1) of MyData;
--	Below does NOT work in MP2, but does in other VHDL's
	constant MyTable: Table := (
--		3 inputs / 2 outputs
             "00011",   
             "00110",
             "01001", 
             "01100",
             "10011",   
             "10110",
             "11001", 
             "11101"
	        );
	 begin
		process(A)
		variable X: MyData;
		begin
			for Count in 0 to Rows-1 loop
				X := MyTable(Count);
				if (A=X(4 downto 2)) then
					B <= X(1 downto 0);
				end if;
			end loop;       
		end process;
end behavior;