-- This routine does not function in MaxPlus2
library ieee;
use ieee.std_logic_1164.all;
entity WAIT_ON is port(
		Clk:	in	std_logic;
		J,K:	in std_logic;
		Q: 	buffer std_logic);
end WAIT_ON;
architecture behavior of WAIT_ON is
begin
	JK_Lat: process (Clk) begin
		if rising_edge(Clk) then 
			if 	(J='0' and K='0') then Q <= Q;
				elsif	(J='0' and K='1') then Q <= '0';
				elsif	(J='1' and K='0') then Q <= '1';
				else	Q <= not(Q);
			end if;
		end if;
		wait on Clk;
	end process JK_Lat;
end behavior;