Notice that when the horizontal counter = 0, it is pointing at the
first displayable pixel on a scan line. When it = 639 it is pointing at
the last displayable pixel on a scan line (H_DISP_END). Similarly, when 
the vertical counter = 0, it is pointing at the first horizontal line 
that has displayable pixels on it. When its count = 479, it is pointing
at the last displayable horizontal line (V_DISP_END). The sync pulses
are placed after the displayable data in this scheme.

If you plan to test the various signals with the oscilloscope, then use
the probe on the VGA connector, not the FPGA (FLEX). The pins are too 
close together and an output may be destroyed. When looking at the face
of the VGA connector with no monitor connected one sees the pins in the
following arrangement:

                       +-----------------------+
                        \    5  4  3  2  1    /
                         \    10 9  8  7  6  /  High Density
                          \ 15 14 13 12 11  /   DB-15 Connector
                           +---------------+

According to the UP-1 manual, Red <= 1, Green <= 2, Blue <= 3, H Sync <= 13
 V Sync <= 14. The metal shell of the connector is grounded. The LSA probes
can be connected here as well using small bits of wire from the protoboard.

My raster generator has the following entity statement. This seems to make the
proper signals available to the other modules (here the video output module).

entity raster_gen is
port(
        board_clk    : in std_logic;
        horiz_sync   : out std_logic;
        vertical_sync: out std_logic;
        video_on     : out std_logic; 
        h_counter    : out std_logic_vector(9 downto 0);
        v_counter    : out std_logic_vector(9 downto 0)
        );
end raster_gen;

The VHDL libraries used are:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

The video module should be developed as a VHDL behavioral module as requested.

The simplest "white" version may be used to test the raster generator.
It has the form (provided by Dr James Hamblen at Ga Tech):

******************************************************************************

-- put out some constant color data to get a white raster
        red_data   <= '1';
        green_data <= '1';
        blue_data  <= '1';

-- send RGB signal pins to the VGA monitor
--   gate the data into the pipe
        red_pipe   <= red_data and video_on;
        green_pipe <= green_data and video_on;
        blue_pipe  <= blue_data and video_on;

-- put the piped data onto the output pins in sync with the board clock
process
begin
        wait until (board_clk'event and board_clk='1');
        red    <= red_pipe;
        green  <= green_pipe;
        blue   <= blue_pipe;
end process;
*******************************************************************************

This module puts out a "white" picture. The outputs are synchronized to the board
clock (25 MHz). The color bar video module just modifies the behavior shown in
the first 4 lines of this module.