*********************************************************************
* SPI EXAMPLE (MASTER Table data)  3744/4744    EMS * 
*********************************************************************
***************************************************
* GCPU++ 
* Send a TABLE of data to the slave and recevie a 
*	TABLE of data from the slave.
***************************************************
*
***************************************************
** SYMBOL DEFINITIONS
***************************************************
***************************************************
STACK	EQU	$900
SP0CR1	EQU	$D0	; SPI Control Register 1
SP0CR2	EQU	$D1	; SPI Control Register 2
SP0BR	EQU	$D2	; SPI Baud Register
SP0SR	EQU	$D3	; SPI Status Register
SP0DR	EQU	$D5	; SPI Data Register
PORTS	EQU	$D6	; Serial Port Registor 
*			;   SPI: Bits 7-4 SS, SCK, MOSI, MISO
*			;   SCI: Bits 1-0 Tx, Rx
DDRS	EQU	$D7	;DATA DIRECTION REGISTER

RAM	EQU	$0900	; Start of RAM
STK	EQU	$0A00	; User Stack
RAMPROG	EQU	$0970	; Program space in RAM

* MASKS
BIT765	EQU	%11100000
BIT7	EQU	%10000000
BIT642 EQU	%01010100
BIT6	EQU	%01000000
BIT5	EQU	%00100000
BIT4	EQU	%00010000
BIT3	EQU	%00001000
BIT2	EQU	%00000100
BIT53	EQU	%00101000
*
***************************************************
** DATA SECTION
***************************************************
*	ORG	$FFD8
*	DC.W	SPI_ISR	;SPI INTERRUPT VECTOR

	ORG	RAM
* DATAM	DC.B	$12
* DATAS	DS.B	1	; Not necessary

TABLE_M	DC.B	"HELLO!"
SIZE_M	EQU	*-TABLE_M
SIZE_S	EQU	*-TABLE_M
TABLE_S	DC.B	SIZE_S

***************************************************
** MAIN PROGRAM
***************************************************
	ORG	RAMPROG
*--------------------------------------------------
* INITIALIZATION
*--------------------------------------------------
* INITIALIZE STACK & Registers
	LDS	#STACK
*
* ENABLE SPI OUTPUTS
	BSET	DDRS BIT765	;outputs SS-SCK-MOSI
	BCLR	DDRS BIT4	;input MISO
*
* INITIALIZE SPI
*  TURN ON SPI INTERRUPT
*  SET AS MASTER; CPHA=1, CPOL=0; /32 CLOCK RATE
* Bit7 = Disable SPI Interrupt (SPIE)
* Bit6 = Enable SPI system (SPE)
* Bit5 = Single slave, so wired-or not needed (SWOM)
* Bit4 = Set for master (MSTR)
* Bit3 = CPOL=0 (CPOL)
* Bit2 = CPHA=1 (CPHA)
* Note: MSTR must be set at same time or before SPE
	BSET	SP0CR1 BIT642		
	BCLR	SP0CR1 BIT53	

* Set SPI speed (NOT NEEDED FOR THE SLAVE)
	LDAA	#%101		;Speed E/64 = E / X
	STAA	SP0BR 		;  where X = 2^(SPR+1) 
*
* TURN ON INTERRUPT SYSTEM
	CLI
*--------------------------------------------------
* Send out the data
*--------------------------------------------------
	LDY	#Table_M
	LDAB	#SIZE_M
HERE	LDAA	0,Y
	STAA	SP0DR		;Send out data from master
WAIT	BRCLR	SP0SR BIT7, WAIT ;Poll the flag
	LDAA	SP0DR		;Read in data from slave
	STAA	SIZE_M,Y	; ...
	INY
	DECB
	BNE	HERE
*
DONE	BRA	DONE