
start_point		equ	$e000		; address to start the system at

; -------------------= INTERRUPT VECTORS =--------------------
; The interrupt vectors are placed at $FFCE (in monitor ROM)
; on the 6812. To allow the monitor's user to be
; able to use the interrupts tho, we need to redirect them
; to a place where the user can modify them. To do that,
; "fake" vectors of 3 bytes are placed in the beginning
; of internal RAM ($0800). The hard-coded vectors are pointed
; to these ones where the user can put a JMP <addr> 
; instruction. One caveat, though: when the board is
; reset, those fake vectors (the JMP instructions) are
; uninitialized! The user must remember to add their own
; jmp instruction.
;
; The SWI and RESET vectors are hard-coded to go to 
; monitor code.

* All dc.w's had to be changed to dc.w to work with miniIDE (JS)

#ifndef _TESTING_				; _TESTING_ is defined if I am testing
						; this monitor, using another monitor
	org	$ffcc				; _TESTING_ will not be defined if
MOD_UNDER		dc.w	v_MOD_UNDER	; this is being loaded onto an EPROM
	org	$ffca
PACB_OVER		dc.w	v_PACB_OVER
	org	$ffd0
BDLC			dc.w	v_BDLC
ATD			dc.w	v_ATD
RES4			dc.w	$0000
SCI0			dc.w	v_SCI0
SPI_TC			dc.w	v_SPI_TC
PAC_IN_EDGE		dc.w	v_PAC_IN_EDGE
PAC_OVER		dc.w  	v_PAC_OVER
TMR_OVER		dc.w	v_TMR_OVER
T7			dc.w	v_T7
T6			dc.w	v_T6
T5			dc.w	v_T5
T4			dc.w	v_T4
T3			dc.w	v_T3
T2			dc.w	v_T2
T1			dc.w	v_T1
T0			dc.w	v_T0
RTI			dc.w	v_RTI
IRQ			dc.w	v_IRQ
XIRQ			dc.w	v_XIRQ
SWI			dc.w	swi_handler	; this is the routine that handles SWI interupts
TRAP			dc.w	v_TRAP		; for the swi routine, see "swi.asm"
COP_FAIL		dc.w	v_COP_FAIL
COP_CLK_FAIL		dc.w	v_COP_CLK_FAIL
RESET			dc.w	start_point	; this is the address that the monitor
						; begins at on a reset

#endif

; ---- FAKE INTERRUPT VECTORS! ----
; see HC12 documention for further explanation on interupt vectors
; if you are not familiar with pseudo vectors and why they are used

	org	$0800

v_MOD_UNDER		ds.b	3
v_PACB_OVER		ds.b	3
v_BDLC			ds.b	3
v_ATD			ds.b	3
v_SCI0			ds.b	3
v_SPI_TC		ds.b	3
v_PAC_IN_EDGE		ds.b	3
v_PAC_OVER		ds.b	3
v_TMR_OVER		ds.b	3 
v_T7			ds.b	3
v_T6			ds.b	3
v_T5			ds.b	3
v_T4			ds.b	3
v_T3			ds.b	3
v_T2			ds.b	3
v_T1			ds.b	3
v_T0			ds.b	3
v_RTI			ds.b	3
v_IRQ			ds.b	3
v_XIRQ			ds.b	3
v_SWI			ds.b	3
v_TRAP			ds.b	3
v_COP_FAIL		ds.b	3
v_COP_CLK_FAIL		ds.b	3
v_RESET			ds.b	3
