-- Michael Hattermann
-- February 17, 2002
-- EEL5666 - IMDL - Spring 2002
--
--
-- Address Decoding for STEVE
--
--

library ieee;
use ieee.std_logic_1164.all;


entity addrdecode is
port (
	-- Inputs --
	DBE_L:		in std_logic;	-- CPLD pin 21
	A15:		in std_logic;	-- CPLD pin 17
	A14:		in std_logic;	-- CPLD pin 18
	A13:		in std_logic;	-- CPLD pin 19
	A12:		in std_logic;	-- CPLD pin 20
	RESET_L:	in std_logic;	-- CPLD pin 16
	RW:			in std_logic;	-- CPLD pin 14
	ECLK:		in std_logic;	-- CPLD pin 12

	-- Outputs --
	EEPROM_OE_L:		out std_logic;		-- CPLD pin 26
	SRAM_CS_L:			out std_logic;		-- CPLD pin 4
	SEG7_LE_L:			out std_logic;		-- CPLD pin 41
	OUT1_CLK:			out std_logic;		-- CPLD pin 5
	LED1_CLK:			out std_logic;		-- CPLD pin 40
	LED2_CLK:			out std_logic;		-- CPLD pin 6
	IN1_OE_L:			out std_logic;		-- CPLD pin 39
	IN2_OE_L:			out std_logic;		-- CPLD pin 8
	SRAM_OE_L:			out std_logic		-- CPLD pin 37
);
end addrdecode;

architecture behavior of addrdecode is
signal address: std_logic_vector(3 downto 0);
begin
	-- Signal definitions -------------
	address <= A15 & A14 & A13 & A12;


	-- EEPROM Address Decoding ------------------------------------
	ROMDECODE: process(address,RW,DBE_L,RESET_L)
	begin
		-- default ROM to off
		EEPROM_OE_L <= '1';

		-- if address in valid range
		if((DBE_L = '0') AND (RESET_L = '1') AND (RW = '1') AND
		  ((address = "1110") OR
		   (address = "1111"))) then

			-- turn on EEPROM
			EEPROM_OE_L <= '0';
		end if;
	end process ROMDECODE;
	---------------------------------------------------------------


	-- SRAM Address Decoding --------------------------------------
	RAMOEDECODE: process (address,RESET_L,DBE_L)
	begin
		-- default RAM output to off
		SRAM_OE_L <= '1';

		-- if address in valid range and we are reading
		if(((DBE_L = '0') AND (RESET_L = '1')) AND
		  ((address = "1000") OR
		   (address = "1001") OR
		   (address = "1010") OR
		   (address = "1011") OR
		   (address = "1100") OR
		   (address = "1101"))) then

			-- turn on RAM outputs
			SRAM_OE_L <= '0';
		end if;
	end process RAMOEDECODE;

	RAMCSDECODE: process (address,RESET_L)
	begin
		-- default RAM to off
		SRAM_CS_L <= '1';

		-- if address in valid range
		if((RESET_L = '1') AND
		  ((address = "1000") OR
		   (address = "1001") OR
		   (address = "1010") OR
		   (address = "1011") OR
		   (address = "1100") OR
		   (address = "1101"))) then

			-- turn on RAM
			SRAM_CS_L <= '0';
		end if;
	end process RAMCSDECODE;
	---------------------------------------------------------------


	-- 7-Segment Output Port Address Decoding ---------------------
	SEG7DECODE: process(address,RESET_L,ECLK,RW)
	begin
		-- default 7-Seg Port to off
		SEG7_LE_L<= '1';

		-- if address is in valid range
		if((ECLK = '1') AND (RESET_L = '1') AND (RW = '0') AND
		  (address = "0100")) then

			-- turn on 7segment output port
			SEG7_LE_L<= '0';
		end if;
	end process SEG7DECODE;
	---------------------------------------------------------------


	-- Output Port 1 Address Decoding -----------------------------
	OUT1DECODE: process(address,RESET_L,RW,ECLK)
	variable temp: std_logic;
	begin
		-- default the port to off
		temp := '0';

		-- if this is a falling edge e-clock
		if falling_edge(ECLK) then
			-- load data into port
			temp := '1';
		end if;

		-- if we are not in the valid address range
		if(NOT((RESET_L = '1') AND (RW = '0') AND (address = "0101"))) then
			-- turn the port off
			temp := '0';
		end if;

		-- Assign OUT1 clock signal
		OUT1_CLK <= temp;
	end process OUT1DECODE;
	---------------------------------------------------------------


	-- LED 1 Output Port Address Decoding -------------------------
	LED1DECODE: process(address,RESET_L,ECLK,RW)
	variable temp: std_logic;
	begin
		-- default the port to off
		temp := '0';

		-- if this is a falling edge e-clock
		if falling_edge(ECLK) then
			-- load data into port
			temp := '1';
		end if;

		-- if address not in valid range
		if(NOT((RESET_L = '1') AND (RW = '0') AND (address = "0110"))) then
			-- turn the port off
			temp := '0';
		end if;

		-- Assign LED1 clock signal
		LED1_CLK <= temp;
	end process LED1DECODE;
	---------------------------------------------------------------


	-- LED 2 Output Port Address Decoding -------------------------
	LED2DECODE: process(address,RESET_L,ECLK,RW)
	variable temp: std_logic;
	begin
		-- default the port to off
		temp := '0';

		-- if this is a falling edge e-clock
		if falling_edge(ECLK) then
			-- load the data into the port
			temp := '1';
		end if;

		-- if address is not in valid range
		if(NOT((RESET_L = '1') AND (RW = '0') AND (address = "0111"))) then
			-- turn the port off
			temp := '0';
		end if;

		-- Assign LED2 clock signal
		LED2_CLK <= temp;
	end process LED2DECODE;
	---------------------------------------------------------------


	-- Input Port 1 Address Decoding ------------------------------
	IN1DECODE: process(address,RESET_L,RW,DBE_L)
	begin
		-- default the output of the port to off
		IN1_OE_L <= '1';

		-- if address is in valid range
		if((RESET_L = '1') AND (RW = '1') AND (DBE_L = '0') AND
		   (address = "0100")) then

			-- read data from the port
			IN1_OE_L <= '0';
		end if;
	end process IN1DECODE;
	---------------------------------------------------------------


	-- Input Port 2 Address Decoding ------------------------------
	IN2DECODE: process(address,RESET_L,RW,DBE_L)
	begin
		-- default the output of the port to off
		IN2_OE_L <= '1';

		-- if the address is in valid range
		if((RESET_L = '1') AND (RW = '1') AND (DBE_L = '0') AND
			(address = "0101")) then

			-- read data from the port
			IN2_OE_L <= '0';
		end if;
	end process IN2DECODE;
	---------------------------------------------------------------

end behavior;