Project Information      c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 04/14/2002 22:30:06

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

addrdecode2
      EPM7032SLC44-10      8        9        0      9       0           28 %

User Pins:                 8        9        0  



Project Information      c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Primitive 'IN2_OE_L' is stuck at VCC
Warning: Primitive 'IN1_OE_L' is stuck at VCC
Warning: Primitive 'LED2_CLK' is stuck at VCC
Warning: Primitive 'OUT1_CLK' is stuck at VCC


Project Information      c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

addrdecode2@20                    A12
addrdecode2@19                    A13
addrdecode2@18                    A14
addrdecode2@17                    A15
addrdecode2@21                    DBE_L
addrdecode2@12                    ECLK
addrdecode2@39                    IN1_OE_L
addrdecode2@8                     IN2_OE_L
addrdecode2@40                    LED1_CLK
addrdecode2@6                     LED2_CLK
addrdecode2@5                     OUT1_CLK
addrdecode2@16                    RESET_L
addrdecode2@26                    ROM_OE
addrdecode2@14                    R/W
addrdecode2@41                    SEG7_LE_L
addrdecode2@37                    SRAM_CS_L
addrdecode2@4                     SRAM2_CS_L


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

***** Logic for device 'addrdecode2' compiled without errors.




Device: EPM7032SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                      S                          
                      R                    S     
                L  O  A                    E  L  
                E  U  M                    G  E  
                D  T  2                    7  D  
                2  1  _                    _  1  
                _  _  C                    L  _  
                C  C  S  V  G  G  G  G  G  E  C  
                L  L  _  C  N  N  N  N  N  _  L  
                K  K  L  C  D  D  D  D  D  L  K  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
      #TDI |  7                                39 | IN1_OE_L 
  IN2_OE_L |  8                                38 | #TDO 
  RESERVED |  9                                37 | SRAM_CS_L 
       GND | 10                                36 | RESERVED 
  RESERVED | 11                                35 | VCC 
      ECLK | 12        EPM7032SLC44-10         34 | RESERVED 
      #TMS | 13                                33 | RESERVED 
       R/W | 14                                32 | #TCK 
       VCC | 15                                31 | RESERVED 
   RESET_L | 16                                30 | GND 
       A15 | 17                                29 | RESERVED 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                A  A  A  D  G  V  R  R  R  R  R  
                1  1  1  B  N  C  E  E  O  E  E  
                4  3  2  E  D  C  S  S  M  S  S  
                         _        E  E  _  E  E  
                         L        R  R  O  R  R  
                                  V  V  E  V  V  
                                  E  E     E  E  
                                  D  D     D  D  
                                                 
                                                 


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     4/16( 25%)  14/16( 87%)   0/16(  0%)   7/36( 19%) 
B:    LC17 - LC32     5/16( 31%)   7/16( 43%)   0/16(  0%)   8/36( 22%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            21/32     ( 65%)
Total logic cells used:                          9/32     ( 28%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                    9/32     ( 28%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  3.66
Total fan-in:                                    33

Total input pins required:                       8
Total fast input logic cells required:           0
Total output pins required:                      9
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                      9
Total flipflops required:                        0
Total product terms required:                   11
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  20   (15)  (A)      INPUT               0      0   0    0    0    2    0  A12
  19   (14)  (A)      INPUT               0      0   0    0    0    4    0  A13
  18   (13)  (A)      INPUT               0      0   0    0    0    5    0  A14
  17   (12)  (A)      INPUT               0      0   0    0    0    5    0  A15
  21   (16)  (A)      INPUT               0      0   0    0    0    3    0  DBE_L
  12    (8)  (A)      INPUT               0      0   0    0    0    4    0  ECLK
  16   (11)  (A)      INPUT               0      0   0    0    0    5    0  RESET_L
  14   (10)  (A)      INPUT               0      0   0    0    0    5    0  R/W


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     19    B     OUTPUT      t        0      0   0    0    0    0    0  IN1_OE_L
   8      5    A     OUTPUT      t        0      0   0    0    0    0    0  IN2_OE_L
  40     18    B     OUTPUT      t        0      0   0    7    0    0    0  LED1_CLK
   6      3    A     OUTPUT      t        0      0   0    0    0    0    0  LED2_CLK
   5      2    A     OUTPUT      t        0      0   0    0    0    0    0  OUT1_CLK
  26     30    B     OUTPUT      t        0      0   0    6    0    0    0  ROM_OE
  41     17    B     OUTPUT      t        0      0   0    7    0    0    0  SEG7_LE_L
  37     21    B     OUTPUT      t        0      0   0    6    0    0    0  SRAM_CS_L
   4      1    A     OUTPUT      t        0      0   0    7    0    0    0  SRAM2_CS_L


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                 Logic cells placed in LAB 'A'
        +------- LC5 IN2_OE_L
        | +----- LC3 LED2_CLK
        | | +--- LC2 OUT1_CLK
        | | | +- LC1 SRAM2_CS_L
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'A'
LC      | | | | | A B |     Logic cells that feed LAB 'A':

Pin
19   -> - - - * | * * | <-- A13
18   -> - - - * | * * | <-- A14
17   -> - - - * | * * | <-- A15
21   -> - - - * | * * | <-- DBE_L
12   -> - - - * | * * | <-- ECLK
16   -> - - - * | * * | <-- RESET_L
14   -> - - - * | * * | <-- R/W


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                   Logic cells placed in LAB 'B'
        +--------- LC19 IN1_OE_L
        | +------- LC18 LED1_CLK
        | | +----- LC30 ROM_OE
        | | | +--- LC17 SEG7_LE_L
        | | | | +- LC21 SRAM_CS_L
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'B'
LC      | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
20   -> - * - * - | - * | <-- A12
19   -> - * * * - | * * | <-- A13
18   -> - * * * * | * * | <-- A14
17   -> - * * * * | * * | <-- A15
21   -> - - * - * | * * | <-- DBE_L
12   -> - * - * * | * * | <-- ECLK
16   -> - * * * * | * * | <-- RESET_L
14   -> - * * * * | * * | <-- R/W


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt
addrdecode2

** EQUATIONS **

A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
DBE_L    : INPUT;
ECLK     : INPUT;
RESET_L  : INPUT;
R/W      : INPUT;

-- Node name is 'IN1_OE_L' 
-- Equation name is 'IN1_OE_L', location is LC019, type is output.
 IN1_OE_L = LCELL( GND $  VCC);

-- Node name is 'IN2_OE_L' 
-- Equation name is 'IN2_OE_L', location is LC005, type is output.
 IN2_OE_L = LCELL( GND $  VCC);

-- Node name is 'LED1_CLK' 
-- Equation name is 'LED1_CLK', location is LC018, type is output.
 LED1_CLK = LCELL( _EQ001 $  VCC);
  _EQ001 = !A12 &  A13 &  A14 & !A15 &  ECLK &  RESET_L & !R/W;

-- Node name is 'LED2_CLK' 
-- Equation name is 'LED2_CLK', location is LC003, type is output.
 LED2_CLK = LCELL( GND $  VCC);

-- Node name is 'OUT1_CLK' 
-- Equation name is 'OUT1_CLK', location is LC002, type is output.
 OUT1_CLK = LCELL( GND $  VCC);

-- Node name is 'ROM_OE' 
-- Equation name is 'ROM_OE', location is LC030, type is output.
 ROM_OE  = LCELL( _EQ002 $  VCC);
  _EQ002 =  A13 &  A14 &  A15 & !DBE_L &  RESET_L &  R/W;

-- Node name is 'SEG7_LE_L' 
-- Equation name is 'SEG7_LE_L', location is LC017, type is output.
 SEG7_LE_L = LCELL( _EQ003 $  VCC);
  _EQ003 = !A12 & !A13 &  A14 & !A15 &  ECLK &  RESET_L & !R/W;

-- Node name is 'SRAM_CS_L' 
-- Equation name is 'SRAM_CS_L', location is LC021, type is output.
 SRAM_CS_L = LCELL( _EQ004 $  VCC);
  _EQ004 = !A14 &  A15 &  ECLK &  RESET_L & !R/W
         # !A14 &  A15 & !DBE_L &  RESET_L &  R/W;

-- Node name is 'SRAM2_CS_L' 
-- Equation name is 'SRAM2_CS_L', location is LC001, type is output.
 SRAM2_CS_L = LCELL( _EQ005 $  VCC);
  _EQ005 = !A13 &  A14 &  A15 &  ECLK &  RESET_L & !R/W
         # !A13 &  A14 &  A15 & !DBE_L &  RESET_L &  R/W;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information      c:\5666\4744 hc12 board\cpld programs\addrdecode2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = FAST

      Logic option settings in 'FAST' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = off
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = off
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 10

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,822K
