Project Informationc:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 02/17/2002 21:21:49

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

rom_decode1-2
      EPM7032SLC44-10      6        1        0      1       0           3  %

User Pins:                 6        1        0  



Project Informationc:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

rom_decode1-2@19                  A13
rom_decode1-2@18                  A14
rom_decode1-2@17                  A15
rom_decode1-2@21                  DBE
rom_decode1-2@16                  Reset
rom_decode1-2@26                  ROM_OE
rom_decode1-2@14                  R/W


Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

***** Logic for device 'rom_decode1-2' compiled without errors.




Device: EPM7032SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

              R  R  R                    R  R  
              E  E  E                    E  E  
              S  S  S                    S  S  
              E  E  E                    E  E  
              R  R  R                    R  R  
              V  V  V  V  G  G  G  G  G  V  V  
              E  E  E  C  N  N  N  N  N  E  E  
              D  D  D  C  D  D  D  D  D  D  D  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | RESERVED 
RESERVED |  8                                38 | #TDO 
RESERVED |  9                                37 | RESERVED 
     GND | 10                                36 | RESERVED 
RESERVED | 11                                35 | VCC 
RESERVED | 12        EPM7032SLC44-10         34 | RESERVED 
    #TMS | 13                                33 | RESERVED 
     R/W | 14                                32 | #TCK 
     VCC | 15                                31 | RESERVED 
   Reset | 16                                30 | GND 
     A15 | 17                                29 | RESERVED 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              A  A  R  D  G  V  R  R  R  R  R  
              1  1  E  B  N  C  E  E  O  E  E  
              4  3  S  E  D  C  S  S  M  S  S  
                    E           E  E  _  E  E  
                    R           R  R  O  R  R  
                    V           V  V  E  V  V  
                    E           E  E     E  E  
                    D           D  D     D  D  


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   8/16( 50%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     1/16(  6%)   3/16( 18%)   0/16(  0%)   6/36( 16%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            11/32     ( 34%)
Total logic cells used:                          1/32     (  3%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                    1/32     (  3%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  6.00
Total fan-in:                                     6

Total input pins required:                       6
Total fast input logic cells required:           0
Total output pins required:                      1
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                      1
Total flipflops required:                        0
Total product terms required:                    1
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  19   (14)  (A)      INPUT               0      0   0    0    0    1    0  A13
  18   (13)  (A)      INPUT               0      0   0    0    0    1    0  A14
  17   (12)  (A)      INPUT               0      0   0    0    0    1    0  A15
  21   (16)  (A)      INPUT               0      0   0    0    0    1    0  DBE
  16   (11)  (A)      INPUT               0      0   0    0    0    1    0  Reset
  14   (10)  (A)      INPUT               0      0   0    0    0    1    0  R/W


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  26     30    B     OUTPUT      t        0      0   0    6    0    0    0  ROM_OE


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC30 ROM_OE
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B |     Logic cells that feed LAB 'B':

Pin
19   -> * | - * | <-- A13
18   -> * | - * | <-- A14
17   -> * | - * | <-- A15
21   -> * | - * | <-- DBE
16   -> * | - * | <-- Reset
14   -> * | - * | <-- R/W


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt
rom_decode1-2

** EQUATIONS **

A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
DBE      : INPUT;
Reset    : INPUT;
R/W      : INPUT;

-- Node name is 'ROM_OE' 
-- Equation name is 'ROM_OE', location is LC030, type is output.
 ROM_OE  = LCELL( _EQ001 $  VCC);
  _EQ001 =  A13 &  A14 &  A15 & !DBE &  Reset &  R/W;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Informationc:\windows\desktop\5666\4744 hc12 board\cpld programs\rom_decode1-2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,545K
