memtest.lst - generated by MGTEK Assembler ASM12 V1.16 Build 101 for WIN32 (x86) - Wed Mar 20 00:22:27 2002 1: * Filename : MEMTEST.ASM 2: * Programmer : Michael Hattermann 3: * Date : February 23, 2002 4: * Version : 1.0 5: * Description : This file contains a program to test 6: * RAM to see if it is working properly. 7: * It displays working address ranges of 8: * RAM between 8000 and FFFF in the 9: * memory map. 10: * 11: * 12: * 13: 14: #include "hc12.asm" 1: * Filename : HC12.H 2: * Programmer : Michael Hattermann 3: * Date : February 21, 2002 4: * Version : 1.0 5: * Description : This file contains equates for the HC12 6: * processor 7: * 8: * 9: ************************************************************ 10: * Register Equates 11: ************************************************************ 12: * 13: #ifndef __HC12_ASM_ 14: =00000001 #define __HC12_ASM_ 1 15: 16: =00000000 IO_BASE EQU 0 17: 18: =00000000 PORTA EQU (IO_BASE + $00) 19: =00000001 PORTB EQU (IO_BASE + $01) 20: =00000002 DDRA EQU (IO_BASE + $02) 21: =00000003 DDRB EQU (IO_BASE + $03) 22: =00000008 PORTE EQU (IO_BASE + $08) 23: =00000009 DDRE EQU (IO_BASE + $09) 24: =0000000A PEAR EQU (IO_BASE + $0A) 25: =0000000B MODE EQU (IO_BASE + $0B) 26: =0000000C PUCR EQU (IO_BASE + $0C) 27: =0000000D RDRIV EQU (IO_BASE + $0D) 28: =00000010 INITRM EQU (IO_BASE + $10) 29: =00000011 INITRG EQU (IO_BASE + $11) 30: =00000012 INITEE EQU (IO_BASE + $12) 31: =00000013 MISC EQU (IO_BASE + $13) 32: =00000014 RTICTL EQU (IO_BASE + $14) 33: =00000015 RTIFLG EQU (IO_BASE + $15) 34: =00000016 COPCTL EQU (IO_BASE + $16) 35: =00000017 COPRST EQU (IO_BASE + $17) 36: =0000001E INTCR EQU (IO_BASE + $1E) 37: =0000001F HPRIO EQU (IO_BASE + $1F) 38: =00000020 BRKCT0 EQU (IO_BASE + $20) 39: =00000021 BRKCT1 EQU (IO_BASE + $21) 40: =00000022 BRKAH EQU (IO_BASE + $22) 41: =00000023 BRKAL EQU (IO_BASE + $23) 42: =00000024 BRKDH EQU (IO_BASE + $24) 43: =00000025 BRKDL EQU (IO_BASE + $25) 44: =00000040 PWCLK EQU (IO_BASE + $40) 45: =00000041 PWPOL EQU (IO_BASE + $41) 46: =00000042 PWEN EQU (IO_BASE + $42) 47: =00000043 PWPRES EQU (IO_BASE + $43) 48: =00000044 PWSCAL0 EQU (IO_BASE + $44) 49: =00000045 PWSCNT0 EQU (IO_BASE + $45) 50: =00000046 PWSCAL1 EQU (IO_BASE + $46) 51: =00000047 PWSCNT1 EQU (IO_BASE + $47) 52: =00000048 PWCNT0 EQU (IO_BASE + $48) 53: =00000049 PWCNT1 EQU (IO_BASE + $49) 54: =0000004A PWCNT2 EQU (IO_BASE + $4A) 55: =0000004B PWCNT3 EQU (IO_BASE + $4B) 56: =0000004C PWPER0 EQU (IO_BASE + $4C) 57: =0000004D PWPER1 EQU (IO_BASE + $4D) 58: =0000004E PWPER2 EQU (IO_BASE + $4E) 59: =0000004F PWPER3 EQU (IO_BASE + $4F) 60: =00000050 PWDTY0 EQU (IO_BASE + $50) 61: =00000051 PWDTY1 EQU (IO_BASE + $51) 62: =00000052 PWDTY2 EQU (IO_BASE + $52) 63: =00000053 PWDTY3 EQU (IO_BASE + $53) 64: =00000054 PWCTL EQU (IO_BASE + $54) 65: =00000055 PWTST EQU (IO_BASE + $55) 66: =00000056 PORTP EQU (IO_BASE + $56) 67: =00000057 DDRP EQU (IO_BASE + $57) 68: =00000060 ATDCTL0 EQU (IO_BASE + $60) 69: =00000061 ATDCTL1 EQU (IO_BASE + $61) 70: =00000062 ATDCTL2 EQU (IO_BASE + $62) 71: =00000063 ATDCTL3 EQU (IO_BASE + $63) 72: =00000064 ATDCTL4 EQU (IO_BASE + $64) 73: =00000065 ATDCTL5 EQU (IO_BASE + $65) 74: =00000066 ATDSTAT EQU (IO_BASE + $66) 75: =00000066 ATDSTATH EQU (IO_BASE + $66) 76: =00000067 ATDSTATL EQU (IO_BASE + $67) 77: =00000068 ATDTST EQU (IO_BASE + $68) 78: =00000068 ATDTSTH EQU (IO_BASE + $68) 79: =00000069 ATDTSTL EQU (IO_BASE + $69) 80: =0000006F PORTAD EQU (IO_BASE + $6F) 81: =00000070 ADR0 EQU (IO_BASE + $70) 82: =00000070 ADR0H EQU (IO_BASE + $70) 83: =00000071 ADR0L EQU (IO_BASE + $71) 84: =00000072 ADR1 EQU (IO_BASE + $72) 85: =00000072 ADR1H EQU (IO_BASE + $72) 86: =00000073 ADR1L EQU (IO_BASE + $73) 87: =00000074 ADR2 EQU (IO_BASE + $74) 88: =00000074 ADR2H EQU (IO_BASE + $74) 89: =00000075 ADR2L EQU (IO_BASE + $75) 90: =00000076 ADR3 EQU (IO_BASE + $76) 91: =00000076 ADR3H EQU (IO_BASE + $76) 92: =00000077 ADR3L EQU (IO_BASE + $77) 93: =00000078 ADR4 EQU (IO_BASE + $78) 94: =00000078 ADR4H EQU (IO_BASE + $78) 95: =00000079 ADR4L EQU (IO_BASE + $79) 96: =0000007A ADR5 EQU (IO_BASE + $7A) 97: =0000007A ADR5H EQU (IO_BASE + $7A) 98: =0000007B ADR5L EQU (IO_BASE + $7B) 99: =0000007C ADR6 EQU (IO_BASE + $7C) 100: =0000007C ADR6H EQU (IO_BASE + $7C) 101: =0000007D ADR6L EQU (IO_BASE + $7D) 102: =0000007E ADR7 EQU (IO_BASE + $7E) 103: =0000007E ADR7H EQU (IO_BASE + $7E) 104: =0000007F ADR7L EQU (IO_BASE + $7F) 105: =00000080 TIOS EQU (IO_BASE + $80) 106: =00000081 CFORC EQU (IO_BASE + $81) 107: =00000082 OC7M EQU (IO_BASE + $82) 108: =00000083 OC7D EQU (IO_BASE + $83) 109: =00000084 TCNT EQU (IO_BASE + $84) 110: =00000084 TCNTH EQU (IO_BASE + $84) 111: =00000085 TCNTL EQU (IO_BASE + $85) 112: =00000086 TSCR EQU (IO_BASE + $86) 113: =00000088 TCTL1 EQU (IO_BASE + $88) 114: =00000089 TCTL2 EQU (IO_BASE + $89) 115: =0000008A TCTL3 EQU (IO_BASE + $8A) 116: =0000008B TCTL4 EQU (IO_BASE + $8B) 117: =0000008C TMSK1 EQU (IO_BASE + $8C) 118: =0000008D TMSK2 EQU (IO_BASE + $8D) 119: =0000008E TFLG1 EQU (IO_BASE + $8E) 120: =0000008F TFLG2 EQU (IO_BASE + $8F) 121: =00000090 TC0 EQU (IO_BASE + $90) 122: =00000090 TC0H EQU (IO_BASE + $90) 123: =00000091 TC0L EQU (IO_BASE + $91) 124: =00000092 TC1 EQU (IO_BASE + $92) 125: =00000092 TC1H EQU (IO_BASE + $92) 126: =00000093 TC1L EQU (IO_BASE + $93) 127: =00000094 TC2 EQU (IO_BASE + $94) 128: =00000094 TC2H EQU (IO_BASE + $94) 129: =00000095 TC2L EQU (IO_BASE + $95) 130: =00000096 TC3 EQU (IO_BASE + $96) 131: =00000096 TC3H EQU (IO_BASE + $96) 132: =00000097 TC3L EQU (IO_BASE + $97) 133: =00000098 TC4 EQU (IO_BASE + $98) 134: =00000098 TC4H EQU (IO_BASE + $98) 135: =00000099 TC4L EQU (IO_BASE + $99) 136: =0000009A TC5 EQU (IO_BASE + $9A) 137: =0000009A TC5H EQU (IO_BASE + $9A) 138: =0000009B TC5L EQU (IO_BASE + $9B) 139: =0000009C TC6 EQU (IO_BASE + $9C) 140: =0000009C TC6H EQU (IO_BASE + $9C) 141: =0000009D TC6L EQU (IO_BASE + $9D) 142: =0000009E TC7 EQU (IO_BASE + $9E) 143: =0000009E TC7H EQU (IO_BASE + $9E) 144: =0000009F TC7L EQU (IO_BASE + $9F) 145: =000000A0 PACTL EQU (IO_BASE + $A0) 146: =000000A1 PAFLG EQU (IO_BASE + $A1) 147: =000000A2 PACN3 EQU (IO_BASE + $A2) 148: =000000A3 PACN2 EQU (IO_BASE + $A3) 149: =000000A4 PACN1 EQU (IO_BASE + $A4) 150: =000000A5 PACN0 EQU (IO_BASE + $A5) 151: =000000A6 MCCTL EQU (IO_BASE + $A6) 152: =000000A7 MCFLG EQU (IO_BASE + $A7) 153: =000000A8 ICPACR EQU (IO_BASE + $A8) 154: =000000A9 DLYCT EQU (IO_BASE + $A9) 155: =000000AA ICOVW EQU (IO_BASE + $AA) 156: =000000AB ICSYS EQU (IO_BASE + $AB) 157: =000000AD TIMTST EQU (IO_BASE + $AD) 158: =000000AE PORTT EQU (IO_BASE + $AE) 159: =000000AF DDRT EQU (IO_BASE + $AF) 160: =000000B0 PBCTL EQU (IO_BASE + $B0) 161: =000000B1 PBFLG EQU (IO_BASE + $B1) 162: =000000B2 PA3H EQU (IO_BASE + $B2) 163: =000000B3 PA2H EQU (IO_BASE + $B3) 164: =000000B4 PA1H EQU (IO_BASE + $B4) 165: =000000B5 PA0H EQU (IO_BASE + $B5) 166: =000000B6 MCCNT EQU (IO_BASE + $B6) 167: =000000B6 MCCNTH EQU (IO_BASE + $B6) 168: =000000B7 MCCNTL EQU (IO_BASE + $B7) 169: =000000C0 SC0BD EQU (IO_BASE + $C0) 170: =000000C0 SC0BDH EQU (IO_BASE + $C0) 171: =000000C1 SC0BDL EQU (IO_BASE + $C1) 172: =000000C2 SC0CR1 EQU (IO_BASE + $C2) 173: =000000C3 SC0CR2 EQU (IO_BASE + $C3) 174: =000000C4 SC0SR1 EQU (IO_BASE + $C4) 175: =000000C5 SC0SR2 EQU (IO_BASE + $C5) 176: =000000C6 SC0DRH EQU (IO_BASE + $C6) 177: =000000C7 SC0DRL EQU (IO_BASE + $C7) 178: =000000D0 SP0CR1 EQU (IO_BASE + $D0) 179: =000000D1 SP0CR2 EQU (IO_BASE + $D1) 180: =000000D2 SP0BR EQU (IO_BASE + $D2) 181: =000000D3 SP0SR EQU (IO_BASE + $D3) 182: =000000D5 SP0DR EQU (IO_BASE + $D5) 183: =000000D6 PORTS EQU (IO_BASE + $D6) 184: =000000D7 DDRS EQU (IO_BASE + $D7) 185: =000000DB PURDS EQU (IO_BASE + $DB) 186: =000000E0 SLOW EQU (IO_BASE + $E0) 187: =000000F0 EEMCR EQU (IO_BASE + $F0) 188: =000000F1 EEPROT EQU (IO_BASE + $F1) 189: =000000F2 EETST EQU (IO_BASE + $F2) 190: =000000F3 EEPROG EQU (IO_BASE + $F3) 191: =000000F4 FEELCK EQU (IO_BASE + $F4) 192: =000000F5 FEEMCR EQU (IO_BASE + $F5) 193: =000000F6 FEETST EQU (IO_BASE + $F6) 194: =000000F7 FEECTL EQU (IO_BASE + $F7) 195: =000000F8 BCR1 EQU (IO_BASE + $F8) 196: =000000F9 BSVR EQU (IO_BASE + $F9) 197: =000000FA BCR2 EQU (IO_BASE + $FA) 198: =000000FB BDR EQU (IO_BASE + $FB) 199: =000000FC BARD EQU (IO_BASE + $FC) 200: =000000FD DLCSCR EQU (IO_BASE + $FD) 201: =000000FE PORTDLC EQU (IO_BASE + $FE) 202: =000000FF DDRDLC EQU (IO_BASE + $FF) 203: * 204: ************************************************************ 205: * Interrupt vector addresses 206: ************************************************************ 207: * 208: =0000FFCC MOD_UNDER_IVECT EQU $FFCC 209: =0000FFCA PACB_OVER_IVECT EQU $FFCA 210: =0000FFD0 BDLC_IVECT EQU $FFD0 211: =0000FFD2 ATD_IVECT EQU $FFD2 212: =0000FFD4 RES4_IVECT EQU $FFD4 213: =0000FFD6 SCI0_IVECT EQU $FFD6 214: =0000FFD8 SPI_TC_IVECT EQU $FFD8 215: =0000FFDA PAC_IN_EDGE_IVECT EQU $FFDA 216: =0000FFDC PAC_OVER_IVECT EQU $FFDC 217: =0000FFDE TMR_OVER_IVECT EQU $FFDE 218: =0000FFE0 T7_IVECT EQU $FFE0 219: =0000FFE2 T6_IVECT EQU $FFE2 220: =0000FFE4 T5_IVECT EQU $FFE4 221: =0000FFE6 T4_IVECT EQU $FFE6 222: =0000FFE8 T3_IVECT EQU $FFE8 223: =0000FFEA T2_IVECT EQU $FFEA 224: =0000FFEC T1_IVECT EQU $FFEC 225: =0000FFEE T0_IVECT EQU $FFEE 226: =0000FFF0 RTI_IVECT EQU $FFF0 227: =0000FFF0 IRQ_IVECT EQU $FFF0 228: =0000FFF0 XIRQ_IVECT EQU $FFF0 229: =0000FFF0 SWI_IVECT EQU $FFF0 230: =0000FFF0 TRAP_IVECT EQU $FFF0 231: =0000FFF0 COP_FAIL_IVECT EQU $FFF0 232: =0000FFF0 COP_CLK_FAIL_IVECT EQU $FFF0 233: =0000FFF0 RESET_IVECT EQU $FFF0 234: * 235: ************************************************************ 236: * Pseudointerrupt vector addresses 237: ************************************************************ 238: * 239: =00000800 MOD_UNDER_PVECT EQU $0800 240: =00000803 PACB_OVER_PVECT EQU $0803 241: =00000806 BDLC_PVECT EQU $0806 242: =00000809 ATD_PVECT EQU $0809 243: =0000080C SCI0_PVECT EQU $080C 244: =0000080F SPI_TC_PVECT EQU $080F 245: =00000812 PAC_IN_EDGE_PVECT EQU $0812 246: =00000815 PAC_OVER_PVECT EQU $0815 247: =00000818 TMR_OVER_PVECT EQU $0818 248: =0000081B T7_PVECT EQU $081B 249: =0000081E T6_PVECT EQU $081E 250: =00000821 T5_PVECT EQU $0821 251: =00000824 T4_PVECT EQU $0824 252: =00000827 T3_PVECT EQU $0827 253: =0000082A T2_PVECT EQU $082A 254: =0000082D T1_PVECT EQU $082D 255: =00000830 T0_PVECT EQU $0830 256: =00000833 RTI_PVECT EQU $0833 257: =00000836 IRQ_PVECT EQU $0836 258: =00000839 XIRQ_PVECT EQU $0839 259: =0000083C SWI_PVECT EQU $083C 260: =0000083F TRAP_PVECT EQU $083F 261: =00000842 COP_FAIL_PVECT EQU $0842 262: =00000845 COP_CLK_FAIL_PVECT EQU $0845 263: =00000848 RESET_PVECT EQU $0848 264: =0000084B USERPROG_PVECT EQU $084B 265: * 266: ************************************************************ 267: * Bit Equates 268: ************************************************************ 269: * 270: =00000001 BIT0 EQU %00000001 ; bit 0 271: =000000FE INV0 EQU %11111110 ; inverse of bit 0 272: =00000002 BIT1 EQU %00000010 ; bit 1 273: =000000FD INV1 EQU %11111101 ; inverse of bit 1 274: =00000004 BIT2 EQU %00000100 ; bit 2 275: =000000FB INV2 EQU %11111011 ; inverse of bit 2 276: =00000008 BIT3 EQU %00001000 ; bit 3 277: =000000F7 INV3 EQU %11110111 ; inverse of bit 3 278: =00000010 BIT4 EQU %00010000 ; bit 4 279: =000000EF INV4 EQU %11101111 ; inverse of bit 4 280: =00000020 BIT5 EQU %00100000 ; bit 5 281: =000000DF INV5 EQU %11011111 ; inverse of bit 5 282: =00000040 BIT6 EQU %01000000 ; bit 6 283: =000000BF INV6 EQU %10111111 ; inverse of bit 6 284: =00000080 BIT7 EQU %10000000 ; bit 7 285: =0000007F INV7 EQU %01111111 ; inverse of bit 7 286: * 287: ************************************************************ 288: * Port Equates 289: ************************************************************ 290: * 291: =00004000 SEG7PORT EQU $4000 ; 7-segment display output port 292: =00005000 OUT1PORT EQU $5000 ; Output port 1 293: =00006000 LED1PORT EQU $6000 ; LED Output port 1 294: =00007000 LED2PORT EQU $7000 ; LED Output port 2 295: =00004000 IN1PORT EQU $4000 ; Input port 1 296: =00005000 IN2PORT EQU $5000 ; Input port 2 297: 298: #endif 15: * 16: ************************************************************ 17: * Memtest Equates 18: ************************************************************ 19: * 20: =00008000 STARTADDR EQU $8000 21: 22: * 23: ************************************************************ 24: * Memtest Constants/Variables 25: ************************************************************ 26: * 27: =0000084B ORG USERPROG_PVECT 28: 084B 06 09AB [03] JMP TEST 29: 30: =00000900 ORG $0900 31: #include "sci.asm" 1: * Filename : SCI.ASM 2: * Programmer : Michael Hattermann 3: * Date : February 4, 2002 4: * Version : 1.0 5: * Description : This file contains SCI communication 6: * functions for input and output of 7: * data. The following functions are 8: * available: 9: * 10: * WAIT_TC - wait for transmit complete 11: * SET_BAUD - change the baud rate 12: * TX_ON - turn transmitter on 13: * TX_OFF - turn transmitter off 14: * RX_ON - turn receiver on 15: * RX_OFF - turn receiver off 16: * RX_INT_ON - turn receiver interrupts on 17: * RX_INT_OFF - turn receiver interrupts off 18: * OUTCHAR - prints character to screen 19: * OUTSTR - prints string to screen 20: * INCHARWAIT - waits for character input 21: * INCHAR - get character input if any 22: * OUTNUM - prints number to screen 23: * NIBTOCHAR - prints nibble to screen 24: * OUTADDR - prints 16-bit num to screen 25: * INITSCI - turns on SCI for 9600 baud 26: * 27: * 28: 29: #include "hc12.asm" 1: * Filename : HC12.H 2: * Programmer : Michael Hattermann 3: * Date : February 21, 2002 4: * Version : 1.0 5: * Description : This file contains equates for the HC12 6: * processor 7: * 8: * 9: ************************************************************ 10: * Register Equates 11: ************************************************************ 12: * 13: #ifndef __HC12_ASM_ 298: #endif 30: 31: * 32: ************************************************************ 33: * SCI Equates 34: ************************************************************ 35: * 36: ****Baud rate equates**** 37: =00000000 BAUD19200 EQU 0 38: =00000002 BAUD14400 EQU 2 39: =00000004 BAUD9600 EQU 4 40: =00000006 BAUD4800 EQU 6 41: =00000008 BAUD2400 EQU 8 42: =0000000A BAUD1200 EQU 10 43: =0000000C BAUD600 EQU 12 44: =0000000E BAUD300 EQU 14 45: 46: ****ASCII character equates**** 47: =00000004 EOS EQU $04 ; User-defined End Of String (EOS) character 48: =0000000D CR EQU $0D ; Carriage Return Character 49: =0000000A LF EQU $0A ; Line Feed Character 50: =0000001B ESC EQU $1B ; ESC character 51: 52: * 53: ************************************************************ 54: * SCI Test Program 55: ************************************************************ 56: * 57: #ifdef __DEBUGSCI_ 104: #endif 105: * 106: ************************************************************ 107: * Constant Definitions 108: ************************************************************ 109: * 110: 0900 000D BAUDTBL DC.W 13 ; (0) BAUD rate = 19200 111: 0902 0011 DC.W 17 ; (1) BAUD rate = 14400 112: 0904 001A DC.W 26 ; (2) BAUD rate = 9600 113: 0906 0034 DC.W 52 ; (3) BAUD rate = 4800 114: 0908 0068 DC.W 104 ; (4) BAUD rate = 2400 115: 090A 00D0 DC.W 208 ; (5) BAUD rate = 1200 116: 090C 01A1 DC.W 417 ; (6) BAUD rate = 600 117: 090E 0341 DC.W 833 ; (7) BAUD rate = 300 118: * 119: ******************************************************************************* 120: * SUBROUTINE - WAIT_TC 121: * Description: Waits for the current transmit operation to complete (polls the 122: * TC flag in SCI status register 1) 123: * Input : None. 124: * Output : None. 125: * Destroys : None. 126: * Calls : None. 127: ******************************************************************************* 128: * 129: 0910 WAIT_TC 130: 0910 4F C4 40 FC [04] BRCLR SC0SR1,BIT6,WAIT_TC ; wait until done sending 131: 0914 3D [05] RTS ; Return to caller 132: * 133: * 134: ******************************************************************************* 135: * SUBROUTINE - SET_BAUD 136: * Description: Sets the baud rate to the rate specified in register A. Reg A 137: * can only take on these predefined values: 138: * BAUD19200 = BAUD rate 19200 139: * BAUD14400 = BAUD rate 14400 140: * BAUD9600 = BAUD rate 9600 141: * BAUD4800 = BAUD rate 4800 142: * BAUD2400 = BAUD rate 2400 143: * BAUD1200 = BAUD rate 1200 144: * BAUD600 = BAUD rate 600 145: * BAUD300 = BAUD rate 300 146: * 147: * Input : New baud rate in reg A 148: * Output : None. 149: * Destroys : SC0BDH, SC0BDL. 150: * Calls : None. 151: ******************************************************************************* 152: * 153: 0915 SET_BAUD 154: 0915 34 [02] PSHX ; Preserve reg X 155: 156: 0916 CE 0900 [02] LDX #BAUDTBL ; Load address of baud table 157: 0919 EE E4 [03] LDX A,X ; Load baud rate from table 158: 091B 5E C0 [02] STX SC0BD ; Set baud rate in register 159: 160: 091D 30 [03] PULX ; Restore reg X 161: 091E 3D [05] RTS ; Return to caller 162: * 163: ******************************************************************************* 164: * SUBROUTINE - TX_ON, TX_OFF 165: * Description: Enables transmitter, disables transmitter 166: * Input : None. 167: * Output : None. 168: * Destroys : SC0CR2. 169: * Calls : None. 170: ******************************************************************************* 171: * 172: 091F TX_ON 173: 091F 4C C3 08 [04] BSET SC0CR2,BIT3 ; turn on the transmitter 174: 0922 3D [05] RTS ; return to caller 175: 0923 TX_OFF 176: 0923 4D C3 08 [04] BCLR SC0CR2,BIT3 ; turn off the transmitter 177: 0926 3D [05] RTS ; return to caller 178: * 179: ******************************************************************************* 180: * SUBROUTINE - RX_ON, RX_OFF,RX_INT_ON,RX_INT_OFF 181: * Description: Enables receiver, disables receiver, enables receive interrupts, 182: * disables receive interrupts 183: * Input : None. 184: * Output : None. 185: * Destroys : SC0CR2. 186: * Calls : None. 187: ******************************************************************************* 188: * 189: 0927 RX_ON 190: 0927 4C C3 04 [04] BSET SC0CR2,BIT2 ; turn on the receiver 191: 092A 3D [05] RTS ; return to caller 192: 092B RX_OFF 193: 092B 4D C3 04 [04] BCLR SC0CR2,BIT2 ; turn off the receiver 194: 092E 3D [05] RTS ; return to caller 195: 092F RX_INT_ON 196: 092F 4C C3 20 [04] BSET SC0CR2,BIT5 ; enable receiver interrupts 197: 0932 3D [05] RTS ; return to caller 198: 0933 RX_INT_OFF 199: 0933 4D C3 20 [04] BCLR SC0CR2,BIT5 ; disable receiver interrupts 200: 0936 3D [05] RTS ; return to caller 201: * 202: ************************************************************************ 203: * SUBROUTINE - OUTCHAR 204: * Description: Outputs the character in register A to the screen 205: * Input : Data to be transmitted in register A. 206: * Output : Transmits the data. 207: * Destroys : None. 208: * Calls : WAIT_TC 209: ************************************************************************ 210: * 211: 0937 OUTCHAR 212: 0937 16 0910 [04] JSR WAIT_TC ; wait until transmitter is idle 213: 093A 5A C7 [02] STAA SC0DRL ; output character 214: 093C 3D [05] RTS ; Return from subtoutine 215: * 216: ************************************************************************ 217: * SUBROUTINE - OUTSTR 218: * Description: Outputs the string pointed to by X. String must be 219: * terminated by EOS character. 220: * Input : String to be output in reg X 221: * Output : Transmits the string. 222: * Destroys : None. 223: * Calls : OUTCHAR 224: ************************************************************************ 225: * 226: 093D OUTSTR 227: 093D 36 [02] PSHA ; preserve reg A 228: 093E 34 [02] PSHX ; preserve reg X 229: 093F OUTSTR1 230: 093F A6 30 [03] LDAA 1,X+ ; Get a character (put in reg A) 231: 0941 81 04 [01] CMPA #EOS ; Check if it's EOS 232: 0943 27 05 [03] BEQ OUTSTR2 ; Branch to Done if it's EOS 233: 0945 16 0937 [04] JSR OUTCHAR ; Print the character 234: 0948 20 F5 [03] BRA OUTSTR1 235: 094A OUTSTR2 236: 094A 30 [03] PULX ; restore reg X 237: 094B 32 [03] PULA ; restore reg A 238: 094C 3D [05] RTS ; Return from subtoutine 239: * 240: ************************************************************************ 241: * SUBROUTINE - INCHARWAIT 242: * Description: Waits for a character to be pressed and reads it into 243: * reg A 244: * Input : None 245: * Output : Character pressed in reg. A 246: * Destroys : A. 247: * Calls : None 248: ************************************************************************ 249: * 250: 094D INCHARWAIT 251: 094D 4F C4 20 FC [04] BRCLR SC0SR1,BIT5,INCHARWAIT ; wait until buffer full 252: 0951 96 C7 [03] LDAA SC0DRL ; input character 253: 0953 3D [05] RTS ; Return from subroutine 254: * 255: ************************************************************************ 256: * SUBROUTINE - INCHAR 257: * Description: Checks to see if character recevied - if so returns the 258: * character, if not returns 0 259: * Input : None 260: * Output : Character pressed in reg A; 0 if none 261: * Destroys : A. 262: * Calls : None 263: ************************************************************************ 264: * 265: 0954 INCHAR 266: 0954 4F C4 20 02 [04] BRCLR SC0SR1,BIT5,INCHAR1 ; if there is no data, get out 267: 0958 96 C7 [03] LDAA SC0DRL ; yes, read data 268: 095A INCHAR1 269: 095A 3D [05] RTS ; return to caller 270: * 271: ************************************************************************ 272: * SUBROUTINE - OUTNUM 273: * Description: Outputs the number in register A to the screen 274: * Input : Data to be transmitted in register A. 275: * Output : Transmits the data. 276: * Destroys : None. 277: * Calls : NIBTOCHAR 278: ************************************************************************ 279: * 280: 095B OUTNUM 281: 095B 36 [02] PSHA ; preserve reg A 282: 095C 36 [02] PSHA ; preserve reg A 283: 095D 84 F0 [01] ANDA #%11110000 ; get upper nibble 284: 095F 44 [01] LSRA ; shift it right to get the nibble 285: 0960 44 [01] LSRA 286: 0961 44 [01] LSRA 287: 0962 44 [01] LSRA 288: 0963 16 096E [04] JSR NIBTOCHAR ; change A and print it 289: 0966 32 [03] PULA ; restore reg A 290: 0967 84 0F [01] ANDA #%00001111 ; get lower nibble 291: 0969 16 096E [04] JSR NIBTOCHAR ; change A and print it 292: 096C 32 [03] PULA ; restore reg A 293: 096D 3D [05] RTS ; return to caller 294: * 295: ************************************************************************ 296: * SUBROUTINE - NIBTOCHAR 297: * Description: Converts lower nibble of A to ASCII and prints it 298: * Input : Data to convert in A. 299: * Output : Transmits the data. 300: * Destroys : None. 301: * Calls : OUTCHAR 302: ************************************************************************ 303: * 304: 096E NIBTOCHAR 305: 096E 81 09 [01] CMPA #9 ; is it greater than 9? 306: 0970 2E 04 [03] BGT NIBTOCHAR1 ; if so, print a character 307: 0972 8B 30 [01] ADDA #48 ; if not, print a number starting at 48 ASCII 308: 0974 20 02 [03] BRA NIBTOCHAR2 ; 309: 0976 NIBTOCHAR1 310: 0976 8B 37 [01] ADDA #55 ; if so, print a letter starting at 55 = 65-10 311: 0978 NIBTOCHAR2 312: 0978 16 0937 [04] JSR OUTCHAR ; print it 313: 097B 3D [05] RTS 314: * 315: ************************************************************************ 316: * SUBROUTINE - OUTADDR 317: * Description: Outputs the number in reg X to the screen 318: * Input : Data to print in X. 319: * Output : Transmits the data. 320: * Destroys : None. 321: * Calls : OUTNUM 322: ************************************************************************ 323: * 324: 097C OUTADDR 325: 097C 3B [02] PSHD ; save reg D 326: 097D B7 54 [01] TFR X,D ; load X into D 327: 097F 16 095B [04] JSR OUTNUM ; prints whats in A -- MSB 328: 0982 180F [02] TBA ; B -> A 329: 0984 16 095B [04] JSR OUTNUM ; prints whats in B -- LSB 330: 0987 3A [03] PULD ; restore D 331: 0988 3D [05] RTS ; return to caller 332: * 333: ************************************************************************ 334: * SUBROUTINE - INITSCI 335: * Description: This subroutine initializes the BAUD rate to 9600 and 336: * sets up the SCI port for 1 start bit, 8 data bits and 337: * 1 stop bit. It also enables the transmitter and receiver 338: * Input : None. 339: * Output : Initializes SCI. 340: * Destroys : None. 341: * Calls : SET_BAUD,TX_ON,RX_ON 342: ************************************************************************ 343: * 344: 0989 36 [02] INITSCI PSHA ; save reg A 345: 098A 86 04 [01] LDAA #BAUD9600 ; set the baud rate to 9600 346: 098C 16 0915 [04] JSR SET_BAUD ; 347: 098F 16 091F [04] JSR TX_ON ; turn on the transmitter 348: 0992 16 0927 [04] JSR RX_ON ; turn on the receiver 349: 0995 32 [03] PULA ; restore reg A 350: 0996 3D [05] RTS ; Return from subtoutine 351: * 352: ************************************************************************ 32: 0997 0D 0A DONESTR DC.B CR,LF 33: 0999 57 45 20 41 52 45 DC.B 'WE ARE DONE!!!!' 099F 20 44 4F 4E 45 21 09A5 21 21 21 34: 09A8 0D 0A 04 DC.B CR,LF,EOS 35: 36: * 37: ******************************************************************************* 38: * SUBROUTINE - MEMTEST 39: * Description: Tests memory of working RAM address ranges 40: * Input : None. 41: * Output : None. 42: * Destroys : None. 43: * Calls : None. 44: ******************************************************************************* 45: * 46: 09AB TEST 47: * MOVB #$00,COPCTL ; turn off COP watchdog timer 48: * MOVB #$A0,MODE ; turn off E-clk stretching 49: * MOVB #$00,INITEE ; turn off internal EEPROM 50: 51: 09AB 180B 00 00E0 [04] MOVB #$00,SLOW ; slow bus clock to 2Mhz 52: 53: * LDS #$0bff ; init the stack pointer 54: 55: 09B0 16 0989 [04] JSR INITSCI ; init SCI system 56: 57: 09B3 CE 8000 [02] LDX #STARTADDR ; load the start address to start testing 58: 59: 09B6 86 FF [01] TEST1 LDAA #$FF ; load first test byte 60: 09B8 6A 00 [02] TEST2 STAA 0,X ; write test byte to memory 61: 09BA E6 00 [03] LDAB 0,X ; read test byte from memory 62: 09BC 1817 [02] CBA ; did we read what we wrote? 63: 09BE 26 06 [03] BNE MOVEON ; no, go handle 64: 09C0 04 40 08 [03] TBEQ A,BADMEM ; are we done, then get out 65: 09C3 43 [01] DECA ; decrement loop counter 66: 09C4 20 F2 [03] BRA TEST2 ; continue checking 67: 68: 09C6 04 B5 ED [03] MOVEON IBNE X,TEST1 ; move to next mem byte if not done 69: 09C9 20 2B [03] BRA DONE ; if we are done get out 70: 71: 09CB 16 097C [04] BADMEM JSR OUTADDR ; print bad memory address 72: 09CE 86 2D [01] LDAA #$2D ; print "-" 73: 09D0 16 0937 [04] JSR OUTCHAR ; 74: 75: 09D3 04 85 10 [03] BADLOOP IBEQ X,BADOUT ; move to next addr; if we are done, get out 76: 77: 09D6 86 FF [01] BADTEST1 LDAA #$FF ; load first test byte 78: 09D8 6A 00 [02] BADTEST2 STAA 0,X ; write test byte to memory 79: 09DA E6 00 [03] LDAB 0,X ; read test byte from memory 80: 09DC 1817 [02] CBA ; did we read what we wrote? 81: 09DE 26 06 [03] BNE BADOUT ; no, move to next byte 82: 09E0 04 50 F0 [03] TBEQ A,BADLOOP ; are we done, then get out 83: 09E3 43 [01] DECA ; decrement loop counter 84: 09E4 20 F2 [03] BRA BADTEST2 ; continue checking 85: 86: 09E6 09 [01] BADOUT DEX ; decrement address to last valid 87: 09E7 16 097C [04] JSR OUTADDR ; print address 88: 09EA 86 0D [01] LDAA #CR ; print carrage return 89: 09EC 16 0937 [04] JSR OUTCHAR ; 90: 09EF 86 0A [01] LDAA #LF ; print line feed 91: 09F1 16 0937 [04] JSR OUTCHAR ; 92: 09F4 20 D0 [03] BRA MOVEON ; 93: 94: 09F6 CE 0997 [02] DONE LDX #DONESTR ; print done message 95: 09F9 16 093D [04] JSR OUTSTR ; 96: 09FC 3F [09] SWI 97: 09FD 20 FE [03] HERE BRA HERE ; end of program 98: * 99: ******************************************************************************* Symbols: __hc12_asm_ 00000001 adr0 00000070 adr0h 00000070 adr0l 00000071 adr1 00000072 adr1h 00000072 adr1l 00000073 adr2 00000074 adr2h 00000074 adr2l 00000075 adr3 00000076 adr3h 00000076 adr3l 00000077 adr4 00000078 adr4h 00000078 adr4l 00000079 adr5 0000007a adr5h 0000007a adr5l 0000007b adr6 0000007c adr6h 0000007c adr6l 0000007d adr7 0000007e adr7h 0000007e adr7l 0000007f atd_ivect 0000ffd2 atd_pvect 00000809 atdctl0 00000060 atdctl1 00000061 atdctl2 00000062 atdctl3 00000063 atdctl4 00000064 atdctl5 00000065 atdstat 00000066 atdstath 00000066 atdstatl 00000067 atdtst 00000068 atdtsth 00000068 atdtstl 00000069 badloop *000009d3 badmem *000009cb badout *000009e6 badtest1 000009d6 badtest2 *000009d8 bard 000000fc baud1200 0000000a baud14400 00000002 baud19200 00000000 baud2400 00000008 baud300 0000000e baud4800 00000006 baud600 0000000c baud9600 *00000004 baudtbl *00000900 bcr1 000000f8 bcr2 000000fa bdlc_ivect 0000ffd0 bdlc_pvect 00000806 bdr 000000fb bit0 00000001 bit1 00000002 bit2 *00000004 bit3 *00000008 bit4 00000010 bit5 *00000020 bit6 *00000040 bit7 00000080 brkah 00000022 brkal 00000023 brkct0 00000020 brkct1 00000021 brkdh 00000024 brkdl 00000025 bsvr 000000f9 cforc 00000081 cop_clk_fail_ivect 0000fff0 cop_clk_fail_pvect 00000845 cop_fail_ivect 0000fff0 cop_fail_pvect 00000842 copctl 00000016 coprst 00000017 cr *0000000d ddra 00000002 ddrb 00000003 ddrdlc 000000ff ddre 00000009 ddrp 00000057 ddrs 000000d7 ddrt 000000af dlcscr 000000fd dlyct 000000a9 done *000009f6 donestr *00000997 eemcr 000000f0 eeprog 000000f3 eeprot 000000f1 eetst 000000f2 eos *00000004 esc 0000001b feectl 000000f7 feelck 000000f4 feemcr 000000f5 feetst 000000f6 here *000009fd hprio 0000001f icovw 000000aa icpacr 000000a8 icsys 000000ab in1port 00004000 in2port 00005000 inchar 00000954 inchar1 *0000095a incharwait *0000094d initee 00000012 initrg 00000011 initrm 00000010 initsci *00000989 intcr 0000001e inv0 000000fe inv1 000000fd inv2 000000fb inv3 000000f7 inv4 000000ef inv5 000000df inv6 000000bf inv7 0000007f io_base *00000000 irq_ivect 0000fff0 irq_pvect 00000836 led1port 00006000 led2port 00007000 lf *0000000a mccnt 000000b6 mccnth 000000b6 mccntl 000000b7 mcctl 000000a6 mcflg 000000a7 misc 00000013 mod_under_ivect 0000ffcc mod_under_pvect 00000800 mode 0000000b moveon *000009c6 nibtochar *0000096e nibtochar1 *00000976 nibtochar2 *00000978 oc7d 00000083 oc7m 00000082 out1port 00005000 outaddr *0000097c outchar *00000937 outnum *0000095b outstr *0000093d outstr1 *0000093f outstr2 *0000094a pa0h 000000b5 pa1h 000000b4 pa2h 000000b3 pa3h 000000b2 pac_in_edge_ivect 0000ffda pac_in_edge_pvect 00000812 pac_over_ivect 0000ffdc pac_over_pvect 00000815 pacb_over_ivect 0000ffca pacb_over_pvect 00000803 pacn0 000000a5 pacn1 000000a4 pacn2 000000a3 pacn3 000000a2 pactl 000000a0 paflg 000000a1 pbctl 000000b0 pbflg 000000b1 pear 0000000a porta 00000000 portad 0000006f portb 00000001 portdlc 000000fe porte 00000008 portp 00000056 ports 000000d6 portt 000000ae pucr 0000000c purds 000000db pwclk 00000040 pwcnt0 00000048 pwcnt1 00000049 pwcnt2 0000004a pwcnt3 0000004b pwctl 00000054 pwdty0 00000050 pwdty1 00000051 pwdty2 00000052 pwdty3 00000053 pwen 00000042 pwper0 0000004c pwper1 0000004d pwper2 0000004e pwper3 0000004f pwpol 00000041 pwpres 00000043 pwscal0 00000044 pwscal1 00000046 pwscnt0 00000045 pwscnt1 00000047 pwtst 00000055 rdriv 0000000d res4_ivect 0000ffd4 reset_ivect 0000fff0 reset_pvect 00000848 rti_ivect 0000fff0 rti_pvect 00000833 rtictl 00000014 rtiflg 00000015 rx_int_off 00000933 rx_int_on 0000092f rx_off 0000092b rx_on *00000927 sc0bd *000000c0 sc0bdh 000000c0 sc0bdl 000000c1 sc0cr1 000000c2 sc0cr2 *000000c3 sc0drh 000000c6 sc0drl *000000c7 sc0sr1 *000000c4 sc0sr2 000000c5 sci0_ivect 0000ffd6 sci0_pvect 0000080c seg7port 00004000 set_baud *00000915 slow *000000e0 sp0br 000000d2 sp0cr1 000000d0 sp0cr2 000000d1 sp0dr 000000d5 sp0sr 000000d3 spi_tc_ivect 0000ffd8 spi_tc_pvect 0000080f startaddr *00008000 swi_ivect 0000fff0 swi_pvect 0000083c t0_ivect 0000ffee t0_pvect 00000830 t1_ivect 0000ffec t1_pvect 0000082d t2_ivect 0000ffea t2_pvect 0000082a t3_ivect 0000ffe8 t3_pvect 00000827 t4_ivect 0000ffe6 t4_pvect 00000824 t5_ivect 0000ffe4 t5_pvect 00000821 t6_ivect 0000ffe2 t6_pvect 0000081e t7_ivect 0000ffe0 t7_pvect 0000081b tc0 00000090 tc0h 00000090 tc0l 00000091 tc1 00000092 tc1h 00000092 tc1l 00000093 tc2 00000094 tc2h 00000094 tc2l 00000095 tc3 00000096 tc3h 00000096 tc3l 00000097 tc4 00000098 tc4h 00000098 tc4l 00000099 tc5 0000009a tc5h 0000009a tc5l 0000009b tc6 0000009c tc6h 0000009c tc6l 0000009d tc7 0000009e tc7h 0000009e tc7l 0000009f tcnt 00000084 tcnth 00000084 tcntl 00000085 tctl1 00000088 tctl2 00000089 tctl3 0000008a tctl4 0000008b test *000009ab test1 *000009b6 test2 *000009b8 tflg1 0000008e tflg2 0000008f timtst 000000ad tios 00000080 tmr_over_ivect 0000ffde tmr_over_pvect 00000818 tmsk1 0000008c tmsk2 0000008d trap_ivect 0000fff0 trap_pvect 0000083f tscr 00000086 tx_off 00000923 tx_on *0000091f userprog_pvect *0000084b wait_tc *00000910 xirq_ivect 0000fff0 xirq_pvect 00000839