Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 08/06/2002 16:26:43

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


MEMORYMAPWMICE


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

memorymapwmice
      EPF10K10TC144-3      82     8      0    0         0  %    89       15 %

User Pins:                 82     8      0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

***** Logic for device 'memorymapwmice' compiled without errors.




Device: EPF10K10TC144-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** ERROR SUMMARY **

Info: Chip 'memorymapwmice' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                                         
                                                                                         
                R   R       R         R R R R                                            
                E   E       E         E E E E           c   c       c                    
                S   S       S         S S S S     G     o V o       o                    
                E x E     G E     y V E E E E G   N     n C n       n     V           c  
                R _ R     N R x   _ C R R R R N   D y y d C d       d     C y       x o  
                V 2 V x x D V _ x 2 C V V V V D y I _ _ _ I _       _   y C _   x   _ n  
                E 1 E 1 1 I E 2 1 1 I E E E E I 1 N 2 2 2 N 2 x y x 2 x 1 I 2 x 1 x 2 d  
                D 5 D 3 4 O D 0 5 2 O D D D D O 3 T 0 8 0 T 1 8 5 3 4 5 0 O 1 2 1 0 5 7  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GNDIO 
    VCCINT |  6                                                                         103 | GNDINT 
      y_23 |  7                                                                         102 | outbus0 
        y7 |  8                                                                         101 | y4 
       y12 |  9                                                                         100 | outbus4 
      x_23 | 10                                                                          99 | y15 
        y8 | 11                                                                          98 | x_211 
       x12 | 12                                                                          97 | y_211 
      y_27 | 13                                                                          96 | x4 
      x_27 | 14                                                                          95 | outbus7 
     GNDIO | 15                                                                          94 | VCCIO 
    GNDINT | 16                                                                          93 | VCCINT 
      x_21 | 17                                                                          92 | outbus6 
     x_214 | 18                                                                          91 | x_29 
     y_214 | 19                             EPF10K10TC144-3                              90 | y1 
      x_26 | 20                                                                          89 | x9 
      y_29 | 21                                                                          88 | outbus1 
      y_26 | 22                                                                          87 | x6 
        y6 | 23                                                                          86 | y14 
     VCCIO | 24                                                                          85 | GNDIO 
    VCCINT | 25                                                                          84 | GNDINT 
     cond3 | 26                                                                          83 | cond2 
   cond_22 | 27                                                                          82 | cond4 
     cond1 | 28                                                                          81 | outbus2 
      y_25 | 29                                                                          80 | x_22 
      y_22 | 30                                                                          79 | cond5 
        y2 | 31                                                                          78 | x10 
     x_213 | 32                                                                          77 | ^MSEL0 
     x_210 | 33                                                                          76 | ^MSEL1 
      #TMS | 34                                                                          75 | VCCINT 
  ^nSTATUS | 35                                                                          74 | ^nCONFIG 
     x_212 | 36                                                                          73 | x1 
           |      38  40  42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  _| 
            \   37  39  41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71   | 
             \--------------------------------------------------------------------------- 
                R R R G c y R y V R y c y G c V V c c c G G y o V x y c x G o y y x V c  
                E E E N o _ E _ C E 0 o 1 N o C C s l o N N 9 u C _ 3 o 7 N u _ _ _ C o  
                S S S D n 2 S 2 C S   n 1 D n C C   k n D D   t C 2   n   D t 2 2 2 C n  
                E E E I d 1 E 4 I E   d   I d I I   _ d I I   b I 4   d   I b 1 1 8 I d  
                R R R O _ 5 R   O R   _   O _ N N   2 0 N N   u O     6   O u 3 0   O _  
                V V V   2   V     V   2     2 T T   5   T T   s             s         2  
                E E E   5   E     E   6     7       M         5             3         3  
                D D D       D     D                 H                                    
                                                    z                                    
                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
A2       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
A3       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
A8       8/ 8(100%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      17/22( 77%)   
B5       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
B7       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
C1       8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
C3       8/ 8(100%)   6/ 8( 75%)   2/ 8( 25%)    0/2    0/2      18/22( 81%)   
C5       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       1/22(  4%)   
C8       8/ 8(100%)   6/ 8( 75%)   8/ 8(100%)    0/2    0/2       4/22( 18%)   
C9       8/ 8(100%)   2/ 8( 25%)   6/ 8( 75%)    2/2    0/2       1/22(  4%)   
C11      8/ 8(100%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      17/22( 77%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                            84/96     ( 87%)
Total logic cells used:                         89/576    ( 15%)
Total embedded cells used:                       0/24     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 3.19/4    ( 79%)
Total fan-in:                                 284/2304    ( 12%)

Total input pins required:                      82
Total input I/O cell registers required:         0
Total output pins required:                      8
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     89
Total flipflops required:                        6
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         0/ 576   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      8   8   8   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0     32/0  
 B:      0   0   0   0   8   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0     16/0  
 C:      8   0   8   0   1   0   0   8   8   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0     41/0  

Total:  16   8  16   0   9   0   8  16   8   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0     89/0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  55      -     -    -    --      INPUT  G             0    0    0    0  clk_25MHz
  56      -     -    -    --      INPUT                0    0    0    1  cond0
  28      -     -    C    --      INPUT                0    0    0    1  cond1
  83      -     -    C    --      INPUT                0    0    0    1  cond2
  26      -     -    C    --      INPUT                0    0    0    1  cond3
  82      -     -    C    --      INPUT                0    0    0    1  cond4
  79      -     -    C    --      INPUT                0    0    0    1  cond5
  64      -     -    -    10      INPUT                0    0    0    1  cond6
 109      -     -    -    01      INPUT                0    0    0    1  cond7
 124      -     -    -    --      INPUT                0    0    0    1  cond_20
 122      -     -    -    12      INPUT                0    0    0    1  cond_21
  27      -     -    C    --      INPUT                0    0    0    1  cond_22
  72      -     -    -    04      INPUT                0    0    0    1  cond_23
 118      -     -    -    07      INPUT                0    0    0    1  cond_24
  41      -     -    -    20      INPUT                0    0    0    1  cond_25
  48      -     -    -    15      INPUT                0    0    0    1  cond_26
  51      -     -    -    13      INPUT                0    0    0    1  cond_27
  54      -     -    -    --      INPUT  G             0    0    0    1  cs
 111      -     -    -    02      INPUT                0    0    0    1  x0
  73      -     -    -    02      INPUT                0    0    0    1  x1
 113      -     -    -    03      INPUT                0    0    0    1  x2
 119      -     -    -    08      INPUT                0    0    0    1  x3
  96      -     -    A    --      INPUT                0    0    0    1  x4
 117      -     -    -    06      INPUT                0    0    0    1  x5
  87      -     -    B    --      INPUT                0    0    0    1  x6
  65      -     -    -    09      INPUT                0    0    0    1  x7
 121      -     -    -    10      INPUT                0    0    0    1  x8
  89      -     -    B    --      INPUT                0    0    0    1  x9
  78      -     -    C    --      INPUT                0    0    0    1  x10
 112      -     -    -    03      INPUT                0    0    0    1  x11
  12      -     -    A    --      INPUT                0    0    0    1  x12
 141      -     -    -    22      INPUT                0    0    0    1  x13
 140      -     -    -    21      INPUT                0    0    0    1  x14
 136      -     -    -    19      INPUT                0    0    0    1  x15
 137      -     -    -    19      INPUT                0    0    0    1  x_20
  17      -     -    B    --      INPUT                0    0    0    1  x_21
  80      -     -    C    --      INPUT                0    0    0    1  x_22
  10      -     -    A    --      INPUT                0    0    0    1  x_23
  62      -     -    -    11      INPUT                0    0    0    1  x_24
 110      -     -    -    01      INPUT                0    0    0    1  x_25
  20      -     -    B    --      INPUT                0    0    0    1  x_26
  14      -     -    A    --      INPUT                0    0    0    1  x_27
  70      -     -    -    05      INPUT                0    0    0    1  x_28
  91      -     -    B    --      INPUT                0    0    0    1  x_29
  33      -     -    C    --      INPUT                0    0    0    1  x_210
  98      -     -    A    --      INPUT                0    0    0    1  x_211
  36      -     -    -    24      INPUT                0    0    0    1  x_212
  32      -     -    C    --      INPUT                0    0    0    1  x_213
  18      -     -    B    --      INPUT                0    0    0    1  x_214
 143      -     -    -    24      INPUT                0    0    0    1  x_215
  47      -     -    -    16      INPUT                0    0    0    1  y0
  90      -     -    B    --      INPUT                0    0    0    1  y1
  31      -     -    C    --      INPUT                0    0    0    1  y2
  63      -     -    -    11      INPUT                0    0    0    1  y3
 101      -     -    A    --      INPUT                0    0    0    1  y4
 120      -     -    -    09      INPUT                0    0    0    1  y5
  23      -     -    B    --      INPUT                0    0    0    1  y6
   8      -     -    A    --      INPUT                0    0    0    1  y7
  11      -     -    A    --      INPUT                0    0    0    1  y8
  59      -     -    -    12      INPUT                0    0    0    1  y9
 116      -     -    -    05      INPUT                0    0    0    1  y10
  49      -     -    -    14      INPUT                0    0    0    1  y11
   9      -     -    A    --      INPUT                0    0    0    1  y12
 128      -     -    -    13      INPUT                0    0    0    1  y13
  86      -     -    B    --      INPUT                0    0    0    1  y14
  99      -     -    A    --      INPUT                0    0    0    1  y15
 126      -     -    -    --      INPUT                0    0    0    1  y_20
 114      -     -    -    04      INPUT                0    0    0    1  y_21
  30      -     -    C    --      INPUT                0    0    0    1  y_22
   7      -     -    A    --      INPUT                0    0    0    1  y_23
  44      -     -    -    18      INPUT                0    0    0    1  y_24
  29      -     -    C    --      INPUT                0    0    0    1  y_25
  22      -     -    B    --      INPUT                0    0    0    1  y_26
  13      -     -    A    --      INPUT                0    0    0    1  y_27
 125      -     -    -    --      INPUT                0    0    0    1  y_28
  21      -     -    B    --      INPUT                0    0    0    1  y_29
  69      -     -    -    06      INPUT                0    0    0    1  y_210
  97      -     -    A    --      INPUT                0    0    0    1  y_211
 135      -     -    -    18      INPUT                0    0    0    1  y_212
  68      -     -    -    07      INPUT                0    0    0    1  y_213
  19      -     -    B    --      INPUT                0    0    0    1  y_214
  42      -     -    -    19      INPUT                0    0    0    1  y_215


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
 102      -     -    A    --        TRI                0    1    0    0  outbus0
  88      -     -    B    --        TRI                0    1    0    0  outbus1
  81      -     -    C    --        TRI                0    1    0    0  outbus2
  67      -     -    -    08        TRI                0    1    0    0  outbus3
 100      -     -    A    --        TRI                0    1    0    0  outbus4
  60      -     -    -    12        TRI                0    1    0    0  outbus5
  92      -     -    B    --        TRI                0    1    0    0  outbus6
  95      -     -    A    --        TRI                0    1    0    0  outbus7


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      7     -    C    09       DFFE   +            0    1    0    1  filter1 (:91)
   -      4     -    C    05       DFFE   +            1    0    0    2  filter0 (:92)
   -      5     -    C    09       DFFE                0    4    0   13  state3 (:94)
   -      2     -    C    09       DFFE                0    4    0   13  state2 (:95)
   -      3     -    C    09       DFFE                0    4    0   13  state1 (:96)
   -      6     -    C    09       DFFE                0    4    0   13  state0 (:97)
   -      2     -    C    08       AND2                0    4    0    8  :311
   -      7     -    C    08       AND2                0    4    0    8  :323
   -      1     -    C    08       AND2                0    4    0    8  :335
   -      4     -    C    08       AND2                0    4    0    8  :347
   -      4     -    C    09       AND2                0    4    0    8  :359
   -      5     -    C    08       AND2                0    4    0    8  :371
   -      3     -    C    08       AND2                0    4    0    8  :383
   -      1     -    C    09       AND2                0    4    0    8  :395
   -      6     -    C    08       AND2                0    4    0    8  :407
   -      8     -    C    09        OR2        !       0    2    0    4  :571
   -      8     -    C    08       AND2                0    4    0    8  :829
   -      2     -    C    03        OR2                2    2    0    1  :844
   -      1     -    A    03        OR2                1    2    0    1  :856
   -      2     -    A    03        OR2                1    2    0    1  :868
   -      3     -    A    03        OR2                1    2    0    1  :880
   -      4     -    A    03        OR2                1    2    0    1  :892
   -      5     -    A    03        OR2                1    2    0    1  :904
   -      6     -    A    03        OR2                1    2    0    1  :916
   -      7     -    A    03        OR2                1    2    0    1  :928
   -      8     -    A    03        OR2                1    2    1    0  :940
   -      6     -    C    03        OR2                2    2    0    1  :949
   -      2     -    B    05        OR2                1    2    0    1  :952
   -      3     -    B    05        OR2                1    2    0    1  :955
   -      4     -    B    05        OR2                1    2    0    1  :958
   -      5     -    B    05        OR2                1    2    0    1  :961
   -      6     -    B    05        OR2                1    2    0    1  :964
   -      7     -    B    05        OR2                1    2    0    1  :967
   -      8     -    B    05        OR2                1    2    0    1  :970
   -      1     -    B    05        OR2                1    2    1    0  :973
   -      1     -    C    03        OR2                2    2    0    1  :982
   -      1     -    C    11        OR2                1    2    0    1  :985
   -      2     -    C    11        OR2                1    2    0    1  :988
   -      3     -    C    11        OR2                1    2    0    1  :991
   -      5     -    C    11        OR2                1    2    0    1  :994
   -      6     -    C    11        OR2                1    2    0    1  :997
   -      7     -    C    11        OR2                1    2    0    1  :1000
   -      8     -    C    11        OR2                1    2    0    1  :1003
   -      4     -    C    11        OR2                1    2    1    0  :1006
   -      7     -    C    03        OR2                2    2    0    1  :1015
   -      1     -    A    01        OR2                1    2    0    1  :1018
   -      2     -    A    01        OR2                1    2    0    1  :1021
   -      4     -    A    01        OR2                1    2    0    1  :1024
   -      5     -    A    01        OR2                1    2    0    1  :1027
   -      6     -    A    01        OR2                1    2    0    1  :1030
   -      7     -    A    01        OR2                1    2    0    1  :1033
   -      8     -    A    01        OR2                1    2    0    1  :1036
   -      3     -    A    01        OR2                1    2    1    0  :1039
   -      4     -    C    03        OR2                2    2    0    1  :1048
   -      2     -    A    08        OR2                1    2    0    1  :1051
   -      3     -    A    08        OR2                1    2    0    1  :1054
   -      4     -    A    08        OR2                1    2    0    1  :1057
   -      5     -    A    08        OR2                1    2    0    1  :1060
   -      6     -    A    08        OR2                1    2    0    1  :1063
   -      7     -    A    08        OR2                1    2    0    1  :1066
   -      8     -    A    08        OR2                1    2    0    1  :1069
   -      1     -    A    08        OR2                1    2    1    0  :1072
   -      5     -    C    03        OR2                2    2    0    1  :1081
   -      1     -    C    01        OR2                1    2    0    1  :1084
   -      2     -    C    01        OR2                1    2    0    1  :1087
   -      4     -    C    01        OR2                1    2    0    1  :1090
   -      5     -    C    01        OR2                1    2    0    1  :1093
   -      6     -    C    01        OR2                1    2    0    1  :1096
   -      7     -    C    01        OR2                1    2    0    1  :1099
   -      8     -    C    01        OR2                1    2    0    1  :1102
   -      3     -    C    01        OR2                1    2    1    0  :1105
   -      3     -    C    03        OR2                2    2    0    1  :1114
   -      1     -    B    07        OR2                1    2    0    1  :1117
   -      2     -    B    07        OR2                1    2    0    1  :1120
   -      3     -    B    07        OR2                1    2    0    1  :1123
   -      4     -    B    07        OR2                1    2    0    1  :1126
   -      5     -    B    07        OR2                1    2    0    1  :1129
   -      7     -    B    07        OR2                1    2    0    1  :1132
   -      8     -    B    07        OR2                1    2    0    1  :1135
   -      6     -    B    07        OR2                1    2    1    0  :1138
   -      8     -    C    03        OR2                2    2    0    1  :1147
   -      2     -    A    02        OR2                1    2    0    1  :1150
   -      3     -    A    02        OR2                1    2    0    1  :1153
   -      4     -    A    02        OR2                1    2    0    1  :1156
   -      5     -    A    02        OR2                1    2    0    1  :1159
   -      6     -    A    02        OR2                1    2    0    1  :1162
   -      7     -    A    02        OR2                1    2    0    1  :1165
   -      8     -    A    02        OR2                1    2    0    1  :1168
   -      1     -    A    02        OR2                1    2    1    0  :1171


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      28/ 96( 29%)    17/ 48( 35%)     0/ 48(  0%)   13/16( 81%)      3/16( 18%)     0/16(  0%)
B:      17/ 96( 17%)    11/ 48( 22%)     0/ 48(  0%)   12/16( 75%)      2/16( 12%)     0/16(  0%)
C:      26/ 96( 27%)    22/ 48( 45%)     0/ 48(  0%)   13/16( 81%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
03:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      6/24( 25%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
06:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
07:      8/24( 33%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
08:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
09:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
10:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
11:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
12:      3/24( 12%)     2/4( 50%)      1/4( 25%)       0/4(  0%)
13:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
19:      3/24( 12%)     3/4( 75%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** CLOCK SIGNALS **

Type     Fan-out       Name
LCELL        4         :571
INPUT        2         clk_25MHz


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt
memorymapwmice

** EQUATIONS **

clk_25MHz : INPUT;
cond0    : INPUT;
cond1    : INPUT;
cond2    : INPUT;
cond3    : INPUT;
cond4    : INPUT;
cond5    : INPUT;
cond6    : INPUT;
cond7    : INPUT;
cond_20  : INPUT;
cond_21  : INPUT;
cond_22  : INPUT;
cond_23  : INPUT;
cond_24  : INPUT;
cond_25  : INPUT;
cond_26  : INPUT;
cond_27  : INPUT;
cs       : INPUT;
x0       : INPUT;
x1       : INPUT;
x2       : INPUT;
x3       : INPUT;
x4       : INPUT;
x5       : INPUT;
x6       : INPUT;
x7       : INPUT;
x8       : INPUT;
x9       : INPUT;
x10      : INPUT;
x11      : INPUT;
x12      : INPUT;
x13      : INPUT;
x14      : INPUT;
x15      : INPUT;
x_20     : INPUT;
x_21     : INPUT;
x_22     : INPUT;
x_23     : INPUT;
x_24     : INPUT;
x_25     : INPUT;
x_26     : INPUT;
x_27     : INPUT;
x_28     : INPUT;
x_29     : INPUT;
x_210    : INPUT;
x_211    : INPUT;
x_212    : INPUT;
x_213    : INPUT;
x_214    : INPUT;
x_215    : INPUT;
y0       : INPUT;
y1       : INPUT;
y2       : INPUT;
y3       : INPUT;
y4       : INPUT;
y5       : INPUT;
y6       : INPUT;
y7       : INPUT;
y8       : INPUT;
y9       : INPUT;
y10      : INPUT;
y11      : INPUT;
y12      : INPUT;
y13      : INPUT;
y14      : INPUT;
y15      : INPUT;
y_20     : INPUT;
y_21     : INPUT;
y_22     : INPUT;
y_23     : INPUT;
y_24     : INPUT;
y_25     : INPUT;
y_26     : INPUT;
y_27     : INPUT;
y_28     : INPUT;
y_29     : INPUT;
y_210    : INPUT;
y_211    : INPUT;
y_212    : INPUT;
y_213    : INPUT;
y_214    : INPUT;
y_215    : INPUT;

-- Node name is ':92' = 'filter0' 
-- Equation name is 'filter0', location is LC4_C5, type is buried.
filter0  = DFFE( cs, GLOBAL( clk_25MHz),  VCC,  VCC,  VCC);

-- Node name is ':91' = 'filter1' 
-- Equation name is 'filter1', location is LC7_C9, type is buried.
filter1  = DFFE( filter0, GLOBAL( clk_25MHz),  VCC,  VCC,  VCC);

-- Node name is 'outbus0' 
-- Equation name is 'outbus0', type is output 
outbus0  = TRI(_LC1_A2, GLOBAL(!cs));

-- Node name is 'outbus1' 
-- Equation name is 'outbus1', type is output 
outbus1  = TRI(_LC6_B7, GLOBAL(!cs));

-- Node name is 'outbus2' 
-- Equation name is 'outbus2', type is output 
outbus2  = TRI(_LC3_C1, GLOBAL(!cs));

-- Node name is 'outbus3' 
-- Equation name is 'outbus3', type is output 
outbus3  = TRI(_LC1_A8, GLOBAL(!cs));

-- Node name is 'outbus4' 
-- Equation name is 'outbus4', type is output 
outbus4  = TRI(_LC3_A1, GLOBAL(!cs));

-- Node name is 'outbus5' 
-- Equation name is 'outbus5', type is output 
outbus5  = TRI(_LC4_C11, GLOBAL(!cs));

-- Node name is 'outbus6' 
-- Equation name is 'outbus6', type is output 
outbus6  = TRI(_LC1_B5, GLOBAL(!cs));

-- Node name is 'outbus7' 
-- Equation name is 'outbus7', type is output 
outbus7  = TRI(_LC8_A3, GLOBAL(!cs));

-- Node name is ':97' = 'state0' 
-- Equation name is 'state0', location is LC6_C9, type is buried.
state0   = DFFE( _EQ001, !_LC8_C9,  VCC,  VCC,  VCC);
  _EQ001 =  state2 &  state3
         #  state1 & !state2
         #  state1 &  state3
         # !state0 &  state1
         # !state0 & !state2
         # !state0 &  state3;

-- Node name is ':96' = 'state1' 
-- Equation name is 'state1', location is LC3_C9, type is buried.
state1   = DFFE( _EQ002, !_LC8_C9,  VCC,  VCC,  VCC);
  _EQ002 = !state1 &  state2
         #  state2 &  state3
         # !state0 &  state2
         #  state0 &  state3
         # !state0 & !state3;

-- Node name is ':95' = 'state2' 
-- Equation name is 'state2', location is LC2_C9, type is buried.
state2   = DFFE( _EQ003, !_LC8_C9,  VCC,  VCC,  VCC);
  _EQ003 =  state0 & !state1 & !state3
         # !state0 &  state1 & !state2;

-- Node name is ':94' = 'state3' 
-- Equation name is 'state3', location is LC5_C9, type is buried.
state3   = DFFE( _EQ004, !_LC8_C9,  VCC,  VCC,  VCC);
  _EQ004 = !state1 & !state2 &  state3
         #  state0 &  state1 &  state2 & !state3;

-- Node name is ':311' 
-- Equation name is '_LC2_C8', type is buried 
_LC2_C8  = LCELL( _EQ005);
  _EQ005 =  state0 & !state1 &  state2 & !state3;

-- Node name is ':323' 
-- Equation name is '_LC7_C8', type is buried 
_LC7_C8  = LCELL( _EQ006);
  _EQ006 = !state0 &  state1 & !state2 &  state3;

-- Node name is ':335' 
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = LCELL( _EQ007);
  _EQ007 =  state0 & !state1 & !state2 &  state3;

-- Node name is ':347' 
-- Equation name is '_LC4_C8', type is buried 
_LC4_C8  = LCELL( _EQ008);
  _EQ008 = !state0 & !state1 & !state2 &  state3;

-- Node name is ':359' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ009);
  _EQ009 =  state0 &  state1 &  state2 & !state3;

-- Node name is ':371' 
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = LCELL( _EQ010);
  _EQ010 = !state0 &  state1 & !state2 & !state3;

-- Node name is ':383' 
-- Equation name is '_LC3_C8', type is buried 
_LC3_C8  = LCELL( _EQ011);
  _EQ011 = !state0 & !state1 &  state2 & !state3;

-- Node name is ':395' 
-- Equation name is '_LC1_C9', type is buried 
_LC1_C9  = LCELL( _EQ012);
  _EQ012 =  state0 & !state1 & !state2 & !state3;

-- Node name is ':407' 
-- Equation name is '_LC6_C8', type is buried 
_LC6_C8  = LCELL( _EQ013);
  _EQ013 =  state0 &  state1 & !state2 & !state3;

-- Node name is ':571' 
-- Equation name is '_LC8_C9', type is buried 
!_LC8_C9 = _LC8_C9~NOT;
_LC8_C9~NOT = LCELL( _EQ014);
  _EQ014 =  filter1
         #  filter0;

-- Node name is ':829' 
-- Equation name is '_LC8_C8', type is buried 
_LC8_C8  = LCELL( _EQ015);
  _EQ015 = !state0 &  state1 &  state2 & !state3;

-- Node name is ':844' 
-- Equation name is '_LC2_C3', type is buried 
_LC2_C3  = LCELL( _EQ016);
  _EQ016 =  cond7 &  _LC2_C8
         #  cond_27 &  _LC8_C8;

-- Node name is ':856' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ017);
  _EQ017 =  _LC2_C3 & !_LC7_C8
         #  _LC7_C8 &  y_27;

-- Node name is ':868' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ018);
  _EQ018 =  _LC1_A3 & !_LC1_C8
         #  _LC1_C8 &  y_215;

-- Node name is ':880' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = LCELL( _EQ019);
  _EQ019 =  _LC2_A3 & !_LC4_C8
         #  _LC4_C8 &  y7;

-- Node name is ':892' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = LCELL( _EQ020);
  _EQ020 =  _LC3_A3 & !_LC4_C9
         #  _LC4_C9 &  y15;

-- Node name is ':904' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ021);
  _EQ021 =  _LC4_A3 & !_LC5_C8
         #  _LC5_C8 &  x_27;

-- Node name is ':916' 
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = LCELL( _EQ022);
  _EQ022 = !_LC3_C8 &  _LC5_A3
         #  _LC3_C8 &  x_215;

-- Node name is ':928' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ023);
  _EQ023 = !_LC1_C9 &  _LC6_A3
         #  _LC1_C9 &  x7;

-- Node name is ':940' 
-- Equation name is '_LC8_A3', type is buried 
_LC8_A3  = LCELL( _EQ024);
  _EQ024 = !_LC6_C8 &  _LC7_A3
         #  _LC6_C8 &  x15;

-- Node name is ':949' 
-- Equation name is '_LC6_C3', type is buried 
_LC6_C3  = LCELL( _EQ025);
  _EQ025 =  cond6 &  _LC2_C8
         #  cond_26 &  _LC8_C8;

-- Node name is ':952' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ026);
  _EQ026 =  _LC6_C3 & !_LC7_C8
         #  _LC7_C8 &  y_26;

-- Node name is ':955' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ027);
  _EQ027 = !_LC1_C8 &  _LC2_B5
         #  _LC1_C8 &  y_214;

-- Node name is ':958' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ028);
  _EQ028 =  _LC3_B5 & !_LC4_C8
         #  _LC4_C8 &  y6;

-- Node name is ':961' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ029);
  _EQ029 =  _LC4_B5 & !_LC4_C9
         #  _LC4_C9 &  y14;

-- Node name is ':964' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ030);
  _EQ030 =  _LC5_B5 & !_LC5_C8
         #  _LC5_C8 &  x_26;

-- Node name is ':967' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ031);
  _EQ031 = !_LC3_C8 &  _LC6_B5
         #  _LC3_C8 &  x_214;

-- Node name is ':970' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ032);
  _EQ032 = !_LC1_C9 &  _LC7_B5
         #  _LC1_C9 &  x6;

-- Node name is ':973' 
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = LCELL( _EQ033);
  _EQ033 = !_LC6_C8 &  _LC8_B5
         #  _LC6_C8 &  x14;

-- Node name is ':982' 
-- Equation name is '_LC1_C3', type is buried 
_LC1_C3  = LCELL( _EQ034);
  _EQ034 =  cond5 &  _LC2_C8
         #  cond_25 &  _LC8_C8;

-- Node name is ':985' 
-- Equation name is '_LC1_C11', type is buried 
_LC1_C11 = LCELL( _EQ035);
  _EQ035 =  _LC1_C3 & !_LC7_C8
         #  _LC7_C8 &  y_25;

-- Node name is ':988' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = LCELL( _EQ036);
  _EQ036 = !_LC1_C8 &  _LC1_C11
         #  _LC1_C8 &  y_213;

-- Node name is ':991' 
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = LCELL( _EQ037);
  _EQ037 =  _LC2_C11 & !_LC4_C8
         #  _LC4_C8 &  y5;

-- Node name is ':994' 
-- Equation name is '_LC5_C11', type is buried 
_LC5_C11 = LCELL( _EQ038);
  _EQ038 =  _LC3_C11 & !_LC4_C9
         #  _LC4_C9 &  y13;

-- Node name is ':997' 
-- Equation name is '_LC6_C11', type is buried 
_LC6_C11 = LCELL( _EQ039);
  _EQ039 = !_LC5_C8 &  _LC5_C11
         #  _LC5_C8 &  x_25;

-- Node name is ':1000' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = LCELL( _EQ040);
  _EQ040 = !_LC3_C8 &  _LC6_C11
         #  _LC3_C8 &  x_213;

-- Node name is ':1003' 
-- Equation name is '_LC8_C11', type is buried 
_LC8_C11 = LCELL( _EQ041);
  _EQ041 = !_LC1_C9 &  _LC7_C11
         #  _LC1_C9 &  x5;

-- Node name is ':1006' 
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = LCELL( _EQ042);
  _EQ042 = !_LC6_C8 &  _LC8_C11
         #  _LC6_C8 &  x13;

-- Node name is ':1015' 
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ043);
  _EQ043 =  cond4 &  _LC2_C8
         #  cond_24 &  _LC8_C8;

-- Node name is ':1018' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ044);
  _EQ044 =  _LC7_C3 & !_LC7_C8
         #  _LC7_C8 &  y_24;

-- Node name is ':1021' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ045);
  _EQ045 =  _LC1_A1 & !_LC1_C8
         #  _LC1_C8 &  y_212;

-- Node name is ':1024' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ046);
  _EQ046 =  _LC2_A1 & !_LC4_C8
         #  _LC4_C8 &  y4;

-- Node name is ':1027' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ047);
  _EQ047 =  _LC4_A1 & !_LC4_C9
         #  _LC4_C9 &  y12;

-- Node name is ':1030' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ048);
  _EQ048 =  _LC5_A1 & !_LC5_C8
         #  _LC5_C8 &  x_24;

-- Node name is ':1033' 
-- Equation name is '_LC7_A1', type is buried 
_LC7_A1  = LCELL( _EQ049);
  _EQ049 = !_LC3_C8 &  _LC6_A1
         #  _LC3_C8 &  x_212;

-- Node name is ':1036' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ050);
  _EQ050 = !_LC1_C9 &  _LC7_A1
         #  _LC1_C9 &  x4;

-- Node name is ':1039' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ051);
  _EQ051 = !_LC6_C8 &  _LC8_A1
         #  _LC6_C8 &  x12;

-- Node name is ':1048' 
-- Equation name is '_LC4_C3', type is buried 
_LC4_C3  = LCELL( _EQ052);
  _EQ052 =  cond3 &  _LC2_C8
         #  cond_23 &  _LC8_C8;

-- Node name is ':1051' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = LCELL( _EQ053);
  _EQ053 =  _LC4_C3 & !_LC7_C8
         #  _LC7_C8 &  y_23;

-- Node name is ':1054' 
-- Equation name is '_LC3_A8', type is buried 
_LC3_A8  = LCELL( _EQ054);
  _EQ054 = !_LC1_C8 &  _LC2_A8
         #  _LC1_C8 &  y_211;

-- Node name is ':1057' 
-- Equation name is '_LC4_A8', type is buried 
_LC4_A8  = LCELL( _EQ055);
  _EQ055 =  _LC3_A8 & !_LC4_C8
         #  _LC4_C8 &  y3;

-- Node name is ':1060' 
-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = LCELL( _EQ056);
  _EQ056 =  _LC4_A8 & !_LC4_C9
         #  _LC4_C9 &  y11;

-- Node name is ':1063' 
-- Equation name is '_LC6_A8', type is buried 
_LC6_A8  = LCELL( _EQ057);
  _EQ057 =  _LC5_A8 & !_LC5_C8
         #  _LC5_C8 &  x_23;

-- Node name is ':1066' 
-- Equation name is '_LC7_A8', type is buried 
_LC7_A8  = LCELL( _EQ058);
  _EQ058 = !_LC3_C8 &  _LC6_A8
         #  _LC3_C8 &  x_211;

-- Node name is ':1069' 
-- Equation name is '_LC8_A8', type is buried 
_LC8_A8  = LCELL( _EQ059);
  _EQ059 = !_LC1_C9 &  _LC7_A8
         #  _LC1_C9 &  x3;

-- Node name is ':1072' 
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ060);
  _EQ060 = !_LC6_C8 &  _LC8_A8
         #  _LC6_C8 &  x11;

-- Node name is ':1081' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _EQ061);
  _EQ061 =  cond2 &  _LC2_C8
         #  cond_22 &  _LC8_C8;

-- Node name is ':1084' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ062);
  _EQ062 =  _LC5_C3 & !_LC7_C8
         #  _LC7_C8 &  y_22;

-- Node name is ':1087' 
-- Equation name is '_LC2_C1', type is buried 
_LC2_C1  = LCELL( _EQ063);
  _EQ063 =  _LC1_C1 & !_LC1_C8
         #  _LC1_C8 &  y_210;

-- Node name is ':1090' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ064);
  _EQ064 =  _LC2_C1 & !_LC4_C8
         #  _LC4_C8 &  y2;

-- Node name is ':1093' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ065);
  _EQ065 =  _LC4_C1 & !_LC4_C9
         #  _LC4_C9 &  y10;

-- Node name is ':1096' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = LCELL( _EQ066);
  _EQ066 =  _LC5_C1 & !_LC5_C8
         #  _LC5_C8 &  x_22;

-- Node name is ':1099' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ067);
  _EQ067 = !_LC3_C8 &  _LC6_C1
         #  _LC3_C8 &  x_210;

-- Node name is ':1102' 
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ068);
  _EQ068 = !_LC1_C9 &  _LC7_C1
         #  _LC1_C9 &  x2;

-- Node name is ':1105' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = LCELL( _EQ069);
  _EQ069 = !_LC6_C8 &  _LC8_C1
         #  _LC6_C8 &  x10;

-- Node name is ':1114' 
-- Equation name is '_LC3_C3', type is buried 
_LC3_C3  = LCELL( _EQ070);
  _EQ070 =  cond1 &  _LC2_C8
         #  cond_21 &  _LC8_C8;

-- Node name is ':1117' 
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = LCELL( _EQ071);
  _EQ071 =  _LC3_C3 & !_LC7_C8
         #  _LC7_C8 &  y_21;

-- Node name is ':1120' 
-- Equation name is '_LC2_B7', type is buried 
_LC2_B7  = LCELL( _EQ072);
  _EQ072 =  _LC1_B7 & !_LC1_C8
         #  _LC1_C8 &  y_29;

-- Node name is ':1123' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = LCELL( _EQ073);
  _EQ073 =  _LC2_B7 & !_LC4_C8
         #  _LC4_C8 &  y1;

-- Node name is ':1126' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = LCELL( _EQ074);
  _EQ074 =  _LC3_B7 & !_LC4_C9
         #  _LC4_C9 &  y9;

-- Node name is ':1129' 
-- Equation name is '_LC5_B7', type is buried 
_LC5_B7  = LCELL( _EQ075);
  _EQ075 =  _LC4_B7 & !_LC5_C8
         #  _LC5_C8 &  x_21;

-- Node name is ':1132' 
-- Equation name is '_LC7_B7', type is buried 
_LC7_B7  = LCELL( _EQ076);
  _EQ076 = !_LC3_C8 &  _LC5_B7
         #  _LC3_C8 &  x_29;

-- Node name is ':1135' 
-- Equation name is '_LC8_B7', type is buried 
_LC8_B7  = LCELL( _EQ077);
  _EQ077 = !_LC1_C9 &  _LC7_B7
         #  _LC1_C9 &  x1;

-- Node name is ':1138' 
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = LCELL( _EQ078);
  _EQ078 = !_LC6_C8 &  _LC8_B7
         #  _LC6_C8 &  x9;

-- Node name is ':1147' 
-- Equation name is '_LC8_C3', type is buried 
_LC8_C3  = LCELL( _EQ079);
  _EQ079 =  cond0 &  _LC2_C8
         #  cond_20 &  _LC8_C8;

-- Node name is ':1150' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ080);
  _EQ080 = !_LC7_C8 &  _LC8_C3
         #  _LC7_C8 &  y_20;

-- Node name is ':1153' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = LCELL( _EQ081);
  _EQ081 = !_LC1_C8 &  _LC2_A2
         #  _LC1_C8 &  y_28;

-- Node name is ':1156' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ082);
  _EQ082 =  _LC3_A2 & !_LC4_C8
         #  _LC4_C8 &  y0;

-- Node name is ':1159' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ083);
  _EQ083 =  _LC4_A2 & !_LC4_C9
         #  _LC4_C9 &  y8;

-- Node name is ':1162' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ084);
  _EQ084 =  _LC5_A2 & !_LC5_C8
         #  _LC5_C8 &  x_20;

-- Node name is ':1165' 
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ085);
  _EQ085 = !_LC3_C8 &  _LC6_A2
         #  _LC3_C8 &  x_28;

-- Node name is ':1168' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ086);
  _EQ086 = !_LC1_C9 &  _LC7_A2
         #  _LC1_C9 &  x0;

-- Node name is ':1171' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ087);
  _EQ087 = !_LC6_C8 &  _LC8_A2
         #  _LC6_C8 &  x8;



Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\memorymapwmice.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:02
   Partitioner                            00:00:01
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,586K
