Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 07/10/2002 09:36:40

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


OUTPUTCONTROLER


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

outputcontroler
      EPF10K70RC240-4      41     9      0    0         0  %    41       1  %

User Pins:                 41     9      0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

***** Logic for device 'outputcontroler' compiled without errors.




Device: EPF10K70RC240-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                                                                                         
                                                                                                                                         
                  R R   R R   R   R R R R R R     R R R R                     R R R R   R R R R R R R   R R R R R R R   R R R R R R R R  
                  E E   E E   E   E E E E E E     E E E E             o       E E E E   E E E E E E E   E E E E E E E   E E E E E E E E  
                  S S   S S   S G S S S S S S   V S S S S       G     u       S S S S V S S S S S S S G S S S S S S S V S S S S S S S S  
                  E E r E E   E N E E E E E E c C E E E E       N c r t   c   E E E E C E E E E E E E N E E E E E E E C E E E E E E E E  
                r R R o R R c R D R R R R R R o C R R R R r r c D o o b r o c R R R R C R R R R R R R D R R R R R R R C R R R R R R R R  
                o V V w V V o V I V V V V V V l I V V V V o o o I n w u o n o V V V V I V V V V V V V I V V V V V V V I V V V V V V V V  
                w E E 1 E E l E N E E E E E E 1 N E E E E w w l N d 1 s w d l E E E E N E E E E E E E N E E E E E E E N E E E E E E E E  
                7 D D 1 D D 9 D T D D D D D D 2 T D D D D 4 2 7 T 1 3 5 0 0 8 D D D D T D D D D D D D T D D D D D D D T D D D D D D D D  
              --------------------------------------------------------------------------------------------------------------------------_ 
             / 240 238 236 234 232 230 228 226 224 222 220 218 216 214 212 210 208 206 204 202 200 198 196 194 192 190 188 186 184 182   |_ 
            /    239 237 235 233 231 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 191 189 187 185 183 181    | 
      #TCK |  1                                                                                                                         180 | ^DATA0 
^CONF_DONE |  2                                                                                                                         179 | ^DCLK 
     ^nCEO |  3                                                                                                                         178 | ^nCE 
      #TDO |  4                                                                                                                         177 | #TDI 
    VCCINT |  5                                                                                                                         176 | GNDINT 
  RESERVED |  6                                                                                                                         175 | RESERVED 
  RESERVED |  7                                                                                                                         174 | RESERVED 
  RESERVED |  8                                                                                                                         173 | RESERVED 
  RESERVED |  9                                                                                                                         172 | RESERVED 
    GNDINT | 10                                                                                                                         171 | RESERVED 
  RESERVED | 11                                                                                                                         170 | VCCINT 
  RESERVED | 12                                                                                                                         169 | RESERVED 
  RESERVED | 13                                                                                                                         168 | RESERVED 
  RESERVED | 14                                                                                                                         167 | RESERVED 
  RESERVED | 15                                                                                                                         166 | RESERVED 
    VCCINT | 16                                                                                                                         165 | GNDINT 
  RESERVED | 17                                                                                                                         164 | RESERVED 
  RESERVED | 18                                                                                                                         163 | RESERVED 
  RESERVED | 19                                                                                                                         162 | RESERVED 
  RESERVED | 20                                                                                                                         161 | RESERVED 
  RESERVED | 21                                                                                                                         160 | VCCINT 
    GNDINT | 22                                                                                                                         159 | RESERVED 
  RESERVED | 23                                                                                                                         158 | RESERVED 
  RESERVED | 24                                                                                                                         157 | RESERVED 
  RESERVED | 25                                                                                                                         156 | RESERVED 
  RESERVED | 26                                                                                                                         155 | GNDINT 
    VCCINT | 27                                                                                                                         154 | col13 
  RESERVED | 28                                                                                                                         153 | col4 
     reset | 29                                                                                                                         152 | row12 
      row5 | 30                                                                                                                         151 | cond5 
   outbus4 | 31                                                     EPF10K70RC240-4                                                     150 | VCCINT 
    GNDINT | 32                                                                                                                         149 | col15 
   outbus0 | 33                                                                                                                         148 | col14 
   outbus7 | 34                                                                                                                         147 | row3 
     cond4 | 35                                                                                                                         146 | cond3 
   outbus6 | 36                                                                                                                         145 | GNDINT 
    VCCINT | 37                                                                                                                         144 | row6 
     row14 | 38                                                                                                                         143 | col10 
     col11 | 39                                                                                                                         142 | row10 
      col3 | 40                                                                                                                         141 | col2 
   outbus3 | 41                                                                                                                         140 | VCCINT 
    GNDINT | 42                                                                                                                         139 | cond2 
   outbus2 | 43                                                                                                                         138 | row1 
      row9 | 44                                                                                                                         137 | RESERVED 
   outbus1 | 45                                                                                                                         136 | RESERVED 
  RESERVED | 46                                                                                                                         135 | GNDINT 
    VCCINT | 47                                                                                                                         134 | RESERVED 
  RESERVED | 48                                                                                                                         133 | RESERVED 
  RESERVED | 49                                                                                                                         132 | RESERVED 
  RESERVED | 50                                                                                                                         131 | RESERVED 
  RESERVED | 51                                                                                                                         130 | VCCINT 
    GNDINT | 52                                                                                                                         129 | RESERVED 
  RESERVED | 53                                                                                                                         128 | RESERVED 
  RESERVED | 54                                                                                                                         127 | RESERVED 
  RESERVED | 55                                                                                                                         126 | RESERVED 
  RESERVED | 56                                                                                                                         125 | GNDINT 
    VCCINT | 57                                                                                                                         124 | ^MSEL0 
      #TMS | 58                                                                                                                         123 | ^MSEL1 
     #TRST | 59                                                                                                                         122 | VCCINT 
  ^nSTATUS | 60                                                                                                                         121 | ^nCONFIG 
           |      62  64  66  68  70  72  74  76  78  80  82  84  86  88  90  92  94  96  98 100 102 104 106 108 110 112 114 116 118 120  _| 
            \   61  63  65  67  69  71  73  75  77  79  81  83  85  87  89  91  93  95  97  99 101 103 105 107 109 111 113 115 117 119   | 
             \--------------------------------------------------------------------------------------------------------------------------- 
                c R r R R R R R G R R R R c R R V R R R R c R c G c R R V c r c G R R V R R R R R R R G R R R R R R R V R R R R R R R R  
                o E o E E E E E N E E E E o E E C E E E E o E o N o E E C s o o N E E C E E E E E E E N E E E E E E E C E E E E E E E E  
                n S w S S S S S D S S S S l S S C S S S S l S n D l S S C   w l D S S C S S S S S S S D S S S S S S S C S S S S S S S S  
                d E 1 E E E E E I E E E E 6 E E I E E E E 5 E d I 1 E E I   8 0 I E E I E E E E E E E I E E E E E E E I E E E E E E E E  
                6 R 5 R R R R R N R R R R   R R N R R R R   R 7 N   R R N       N R R N R R R R R R R N R R R R R R R N R R R R R R R R  
                  V   V V V V V T V V V V   V V T V V V V   V   T   V V T       T V V T V V V V V V V T V V V V V V V T V V V V V V V V  
                  E   E E E E E   E E E E   E E   E E E E   E       E E           E E   E E E E E E E   E E E E E E E   E E E E E E E E  
                  D   D D D D D   D D D D   D D   D D D D   D       D D           D D   D D D D D D D   D D D D D D D   D D D D D D D D  
                                                                                                                                         
                                                                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
D42      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       3/26( 11%)   
D44      8/ 8(100%)   5/ 8( 62%)   4/ 8( 50%)    1/2    0/2       1/26(  3%)   
E28      8/ 8(100%)   1/ 8( 12%)   1/ 8( 12%)    0/2    0/2      15/26( 57%)   
E52      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      15/26( 57%)   
F45      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      15/26( 57%)   
G40      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      15/26( 57%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                            44/183    ( 24%)
Total logic cells used:                         41/3744   (  1%)
Total embedded cells used:                       0/72     (  0%)
Total EABs used:                                 0/9      (  0%)
Average fan-in:                                 3.21/4    ( 80%)
Total fan-in:                                 132/14976   (  0%)

Total input pins required:                      41
Total input I/O cell registers required:         0
Total output pins required:                      9
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     41
Total flipflops required:                        3
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         0/3744   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  EA  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 D:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1   0   8   0   0   0   0   0   0   0   0      9/0  
 E:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8     16/0  
 F:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   0   0   0      8/0  
 G:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0      8/0  
 H:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 I:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   8   0   1   0   8   8   0   0   0   0   0   0   8     41/0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  92      -     -    -    --      INPUT                0    0    0    1  col0
  86      -     -    -    29      INPUT                0    0    0    1  col1
 141      -     -    G    --      INPUT                0    0    0    1  col2
  40      -     -    F    --      INPUT                0    0    0    1  col3
 153      -     -    E    --      INPUT                0    0    0    1  col4
  82      -     -    -    32      INPUT                0    0    0    1  col5
  74      -     -    -    39      INPUT                0    0    0    1  col6
 217      -     -    -    31      INPUT                0    0    0    1  col7
 210      -     -    -    --      INPUT                0    0    0    1  col8
 234      -     -    -    45      INPUT                0    0    0    1  col9
 143      -     -    G    --      INPUT                0    0    0    1  col10
  39      -     -    F    --      INPUT                0    0    0    1  col11
 225      -     -    -    37      INPUT                0    0    0    1  col12
 154      -     -    E    --      INPUT                0    0    0    1  col13
 148      -     -    F    --      INPUT                0    0    0    1  col14
 149      -     -    E    --      INPUT                0    0    0    1  col15
 211      -     -    -    --      INPUT                0    0    0    1  cond0
 215      -     -    -    29      INPUT                0    0    0    1  cond1
 139      -     -    G    --      INPUT                0    0    0    1  cond2
 146      -     -    F    --      INPUT                0    0    0    1  cond3
  35      -     -    E    --      INPUT                0    0    0    1  cond4
 151      -     -    E    --      INPUT                0    0    0    1  cond5
  61      -     -    -    52      INPUT                0    0    0    1  cond6
  84      -     -    -    30      INPUT                0    0    0    1  cond7
  90      -     -    -    --      INPUT  G             0    0    0    0  cs
 212      -     -    -    --      INPUT                0    0    0    1  row0
 138      -     -    G    --      INPUT                0    0    0    1  row1
 218      -     -    -    32      INPUT                0    0    0    1  row2
 147      -     -    F    --      INPUT                0    0    0    1  row3
 219      -     -    -    32      INPUT                0    0    0    1  row4
  30      -     -    E    --      INPUT                0    0    0    1  row5
 144      -     -    F    --      INPUT                0    0    0    1  row6
 240      -     -    -    52      INPUT                0    0    0    1  row7
  91      -     -    -    --      INPUT                0    0    0    1  row8
  44      -     -    G    --      INPUT                0    0    0    1  row9
 142      -     -    G    --      INPUT                0    0    0    1  row10
 237      -     -    -    48      INPUT                0    0    0    1  row11
 152      -     -    E    --      INPUT                0    0    0    1  row12
 214      -     -    -    28      INPUT                0    0    0    1  row13
  38      -     -    F    --      INPUT                0    0    0    1  row14
  63      -     -    -    50      INPUT                0    0    0    1  row15


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  33      -     -    E    --        TRI                0    1    0    0  outbus0
  45      -     -    G    --        TRI                0    1    0    0  outbus1
  43      -     -    G    --        TRI                0    1    0    0  outbus2
  41      -     -    F    --        TRI                0    1    0    0  outbus3
  31      -     -    E    --        TRI                0    1    0    0  outbus4
 213      -     -    -    27        TRI                0    1    0    0  outbus5
  36      -     -    F    --        TRI                0    1    0    0  outbus6
  34      -     -    E    --        TRI                0    1    0    0  outbus7
  29      -     -    D    --     OUTPUT                0    1    0    0  reset


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      8     -    D    44       DFFE   +            0    2    0    6  state2 (:51)
   -      1     -    D    42       DFFE   +            0    3    0    7  state1 (:52)
   -      5     -    D    44       DFFE   +            0    4    0    7  state0 (:53)
   -      6     -    D    44       AND2                0    3    0    9  :129
   -      4     -    D    44       AND2                0    3    0    8  :139
   -      3     -    D    44       AND2                0    3    0   10  :149
   -      2     -    D    44       AND2                0    3    0   10  :159
   -      1     -    D    44        OR2        !       0    3    0   10  :169
   -      7     -    D    44        OR2        !       0    3    1    0  :338
   -      6     -    E    52        OR2                2    2    0    1  :428
   -      7     -    E    52        OR2                1    2    0    1  :438
   -      8     -    E    52        OR2                1    2    0    1  :448
   -      5     -    E    52        OR2                1    2    1    0  :458
   -      5     -    F    45        OR2                2    2    0    1  :467
   -      6     -    F    45        OR2                1    2    0    1  :470
   -      7     -    F    45        OR2                1    2    0    1  :473
   -      1     -    F    45        OR2                1    2    1    0  :476
   -      6     -    E    28        OR2                2    2    0    1  :485
   -      7     -    E    28        OR2                1    2    0    1  :488
   -      8     -    E    28        OR2                1    2    0    1  :491
   -      4     -    E    28        OR2                1    2    1    0  :494
   -      1     -    E    52        OR2                2    2    0    1  :503
   -      3     -    E    52        OR2                1    2    0    1  :506
   -      4     -    E    52        OR2                1    2    0    1  :509
   -      2     -    E    52        OR2                1    2    1    0  :512
   -      2     -    F    45        OR2                2    2    0    1  :521
   -      3     -    F    45        OR2                1    2    0    1  :524
   -      4     -    F    45        OR2                1    2    0    1  :527
   -      8     -    F    45        OR2                1    2    1    0  :530
   -      5     -    G    40        OR2                2    2    0    1  :539
   -      7     -    G    40        OR2                1    2    0    1  :542
   -      8     -    G    40        OR2                1    2    0    1  :545
   -      2     -    G    40        OR2                1    2    1    0  :548
   -      1     -    G    40        OR2                2    2    0    1  :557
   -      3     -    G    40        OR2                1    2    0    1  :560
   -      4     -    G    40        OR2                1    2    0    1  :563
   -      6     -    G    40        OR2                1    2    1    0  :566
   -      1     -    E    28        OR2                2    2    0    1  :575
   -      3     -    E    28        OR2                1    2    0    1  :578
   -      5     -    E    28        OR2                1    2    0    1  :581
   -      2     -    E    28        OR2                1    2    1    0  :584


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:       0/208(  0%)     0/104(  0%)     5/104(  4%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
E:       9/208(  4%)     0/104(  0%)    14/104( 13%)    7/16( 43%)      3/16( 18%)     0/16(  0%)
F:       7/208(  3%)     0/104(  0%)    10/104(  9%)    7/16( 43%)      2/16( 12%)     0/16(  0%)
G:       6/208(  2%)     0/104(  0%)    11/104( 10%)    6/16( 37%)      2/16( 12%)     0/16(  0%)
H:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
I:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
28:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
29:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
30:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
31:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
32:      3/24( 12%)     3/4( 75%)      0/4(  0%)       0/4(  0%)
33:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
37:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
38:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
39:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
40:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
41:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
42:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      5/24( 20%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
45:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
46:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
47:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
48:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
49:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
50:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
51:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       11         cs


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt
outputcontroler

** EQUATIONS **

col0     : INPUT;
col1     : INPUT;
col2     : INPUT;
col3     : INPUT;
col4     : INPUT;
col5     : INPUT;
col6     : INPUT;
col7     : INPUT;
col8     : INPUT;
col9     : INPUT;
col10    : INPUT;
col11    : INPUT;
col12    : INPUT;
col13    : INPUT;
col14    : INPUT;
col15    : INPUT;
cond0    : INPUT;
cond1    : INPUT;
cond2    : INPUT;
cond3    : INPUT;
cond4    : INPUT;
cond5    : INPUT;
cond6    : INPUT;
cond7    : INPUT;
cs       : INPUT;
row0     : INPUT;
row1     : INPUT;
row2     : INPUT;
row3     : INPUT;
row4     : INPUT;
row5     : INPUT;
row6     : INPUT;
row7     : INPUT;
row8     : INPUT;
row9     : INPUT;
row10    : INPUT;
row11    : INPUT;
row12    : INPUT;
row13    : INPUT;
row14    : INPUT;
row15    : INPUT;

-- Node name is 'outbus0' 
-- Equation name is 'outbus0', type is output 
outbus0  = TRI(_LC2_E28, GLOBAL(!cs));

-- Node name is 'outbus1' 
-- Equation name is 'outbus1', type is output 
outbus1  = TRI(_LC6_G40, GLOBAL(!cs));

-- Node name is 'outbus2' 
-- Equation name is 'outbus2', type is output 
outbus2  = TRI(_LC2_G40, GLOBAL(!cs));

-- Node name is 'outbus3' 
-- Equation name is 'outbus3', type is output 
outbus3  = TRI(_LC8_F45, GLOBAL(!cs));

-- Node name is 'outbus4' 
-- Equation name is 'outbus4', type is output 
outbus4  = TRI(_LC2_E52, GLOBAL(!cs));

-- Node name is 'outbus5' 
-- Equation name is 'outbus5', type is output 
outbus5  = TRI(_LC4_E28, GLOBAL(!cs));

-- Node name is 'outbus6' 
-- Equation name is 'outbus6', type is output 
outbus6  = TRI(_LC1_F45, GLOBAL(!cs));

-- Node name is 'outbus7' 
-- Equation name is 'outbus7', type is output 
outbus7  = TRI(_LC5_E52, GLOBAL(!cs));

-- Node name is 'reset' 
-- Equation name is 'reset', type is output 
reset    = !_LC7_D44;

-- Node name is ':53' = 'state0' 
-- Equation name is 'state0', location is LC5_D44, type is buried.
state0   = DFFE( _EQ001, GLOBAL(!cs),  VCC,  VCC,  VCC);
  _EQ001 = !_LC2_D44 &  _LC6_D44
         # !_LC2_D44 &  _LC3_D44
         #  _LC1_D44;

-- Node name is ':52' = 'state1' 
-- Equation name is 'state1', location is LC1_D42, type is buried.
state1   = DFFE( _EQ002, GLOBAL(!cs),  VCC,  VCC,  VCC);
  _EQ002 = !_LC1_D44 &  _LC3_D44
         # !_LC1_D44 &  _LC2_D44;

-- Node name is ':51' = 'state2' 
-- Equation name is 'state2', location is LC8_D44, type is buried.
state2   = DFFE( _EQ003, GLOBAL(!cs),  VCC,  VCC,  VCC);
  _EQ003 = !state0 & !state1 &  state2
         #  state0 &  state1 & !state2;

-- Node name is ':129' 
-- Equation name is '_LC6_D44', type is buried 
_LC6_D44 = LCELL( _EQ004);
  _EQ004 = !state0 & !state1 &  state2;

-- Node name is ':139' 
-- Equation name is '_LC4_D44', type is buried 
_LC4_D44 = LCELL( _EQ005);
  _EQ005 =  state0 &  state1 & !state2;

-- Node name is ':149' 
-- Equation name is '_LC3_D44', type is buried 
_LC3_D44 = LCELL( _EQ006);
  _EQ006 = !state0 &  state1 & !state2;

-- Node name is ':159' 
-- Equation name is '_LC2_D44', type is buried 
_LC2_D44 = LCELL( _EQ007);
  _EQ007 =  state0 & !state1 & !state2;

-- Node name is ':169' 
-- Equation name is '_LC1_D44', type is buried 
!_LC1_D44 = _LC1_D44~NOT;
_LC1_D44~NOT = LCELL( _EQ008);
  _EQ008 =  state2
         #  state0
         #  state1;

-- Node name is ':338' 
-- Equation name is '_LC7_D44', type is buried 
!_LC7_D44 = _LC7_D44~NOT;
_LC7_D44~NOT = LCELL( _EQ009);
  _EQ009 = !state0
         #  state1
         # !state2;

-- Node name is ':428' 
-- Equation name is '_LC6_E52', type is buried 
_LC6_E52 = LCELL( _EQ010);
  _EQ010 =  col7 &  _LC6_D44
         #  col15 &  _LC4_D44;

-- Node name is ':438' 
-- Equation name is '_LC7_E52', type is buried 
_LC7_E52 = LCELL( _EQ011);
  _EQ011 = !_LC3_D44 &  _LC6_E52
         #  _LC3_D44 &  row7;

-- Node name is ':448' 
-- Equation name is '_LC8_E52', type is buried 
_LC8_E52 = LCELL( _EQ012);
  _EQ012 = !_LC2_D44 &  _LC7_E52
         #  _LC2_D44 &  row15;

-- Node name is ':458' 
-- Equation name is '_LC5_E52', type is buried 
_LC5_E52 = LCELL( _EQ013);
  _EQ013 = !_LC1_D44 &  _LC8_E52
         #  cond7 &  _LC1_D44;

-- Node name is ':467' 
-- Equation name is '_LC5_F45', type is buried 
_LC5_F45 = LCELL( _EQ014);
  _EQ014 =  col6 &  _LC6_D44
         #  col14 &  _LC4_D44;

-- Node name is ':470' 
-- Equation name is '_LC6_F45', type is buried 
_LC6_F45 = LCELL( _EQ015);
  _EQ015 = !_LC3_D44 &  _LC5_F45
         #  _LC3_D44 &  row6;

-- Node name is ':473' 
-- Equation name is '_LC7_F45', type is buried 
_LC7_F45 = LCELL( _EQ016);
  _EQ016 = !_LC2_D44 &  _LC6_F45
         #  _LC2_D44 &  row14;

-- Node name is ':476' 
-- Equation name is '_LC1_F45', type is buried 
_LC1_F45 = LCELL( _EQ017);
  _EQ017 = !_LC1_D44 &  _LC7_F45
         #  cond6 &  _LC1_D44;

-- Node name is ':485' 
-- Equation name is '_LC6_E28', type is buried 
_LC6_E28 = LCELL( _EQ018);
  _EQ018 =  col5 &  _LC6_D44
         #  col13 &  _LC4_D44;

-- Node name is ':488' 
-- Equation name is '_LC7_E28', type is buried 
_LC7_E28 = LCELL( _EQ019);
  _EQ019 = !_LC3_D44 &  _LC6_E28
         #  _LC3_D44 &  row5;

-- Node name is ':491' 
-- Equation name is '_LC8_E28', type is buried 
_LC8_E28 = LCELL( _EQ020);
  _EQ020 = !_LC2_D44 &  _LC7_E28
         #  _LC2_D44 &  row13;

-- Node name is ':494' 
-- Equation name is '_LC4_E28', type is buried 
_LC4_E28 = LCELL( _EQ021);
  _EQ021 = !_LC1_D44 &  _LC8_E28
         #  cond5 &  _LC1_D44;

-- Node name is ':503' 
-- Equation name is '_LC1_E52', type is buried 
_LC1_E52 = LCELL( _EQ022);
  _EQ022 =  col4 &  _LC6_D44
         #  col12 &  _LC4_D44;

-- Node name is ':506' 
-- Equation name is '_LC3_E52', type is buried 
_LC3_E52 = LCELL( _EQ023);
  _EQ023 =  _LC1_E52 & !_LC3_D44
         #  _LC3_D44 &  row4;

-- Node name is ':509' 
-- Equation name is '_LC4_E52', type is buried 
_LC4_E52 = LCELL( _EQ024);
  _EQ024 = !_LC2_D44 &  _LC3_E52
         #  _LC2_D44 &  row12;

-- Node name is ':512' 
-- Equation name is '_LC2_E52', type is buried 
_LC2_E52 = LCELL( _EQ025);
  _EQ025 = !_LC1_D44 &  _LC4_E52
         #  cond4 &  _LC1_D44;

-- Node name is ':521' 
-- Equation name is '_LC2_F45', type is buried 
_LC2_F45 = LCELL( _EQ026);
  _EQ026 =  col3 &  _LC6_D44
         #  col11 &  _LC4_D44;

-- Node name is ':524' 
-- Equation name is '_LC3_F45', type is buried 
_LC3_F45 = LCELL( _EQ027);
  _EQ027 =  _LC2_F45 & !_LC3_D44
         #  _LC3_D44 &  row3;

-- Node name is ':527' 
-- Equation name is '_LC4_F45', type is buried 
_LC4_F45 = LCELL( _EQ028);
  _EQ028 = !_LC2_D44 &  _LC3_F45
         #  _LC2_D44 &  row11;

-- Node name is ':530' 
-- Equation name is '_LC8_F45', type is buried 
_LC8_F45 = LCELL( _EQ029);
  _EQ029 = !_LC1_D44 &  _LC4_F45
         #  cond3 &  _LC1_D44;

-- Node name is ':539' 
-- Equation name is '_LC5_G40', type is buried 
_LC5_G40 = LCELL( _EQ030);
  _EQ030 =  col2 &  _LC6_D44
         #  col10 &  _LC4_D44;

-- Node name is ':542' 
-- Equation name is '_LC7_G40', type is buried 
_LC7_G40 = LCELL( _EQ031);
  _EQ031 = !_LC3_D44 &  _LC5_G40
         #  _LC3_D44 &  row2;

-- Node name is ':545' 
-- Equation name is '_LC8_G40', type is buried 
_LC8_G40 = LCELL( _EQ032);
  _EQ032 = !_LC2_D44 &  _LC7_G40
         #  _LC2_D44 &  row10;

-- Node name is ':548' 
-- Equation name is '_LC2_G40', type is buried 
_LC2_G40 = LCELL( _EQ033);
  _EQ033 = !_LC1_D44 &  _LC8_G40
         #  cond2 &  _LC1_D44;

-- Node name is ':557' 
-- Equation name is '_LC1_G40', type is buried 
_LC1_G40 = LCELL( _EQ034);
  _EQ034 =  col1 &  _LC6_D44
         #  col9 &  _LC4_D44;

-- Node name is ':560' 
-- Equation name is '_LC3_G40', type is buried 
_LC3_G40 = LCELL( _EQ035);
  _EQ035 =  _LC1_G40 & !_LC3_D44
         #  _LC3_D44 &  row1;

-- Node name is ':563' 
-- Equation name is '_LC4_G40', type is buried 
_LC4_G40 = LCELL( _EQ036);
  _EQ036 = !_LC2_D44 &  _LC3_G40
         #  _LC2_D44 &  row9;

-- Node name is ':566' 
-- Equation name is '_LC6_G40', type is buried 
_LC6_G40 = LCELL( _EQ037);
  _EQ037 = !_LC1_D44 &  _LC4_G40
         #  cond1 &  _LC1_D44;

-- Node name is ':575' 
-- Equation name is '_LC1_E28', type is buried 
_LC1_E28 = LCELL( _EQ038);
  _EQ038 =  col0 &  _LC6_D44
         #  col8 &  _LC4_D44;

-- Node name is ':578' 
-- Equation name is '_LC3_E28', type is buried 
_LC3_E28 = LCELL( _EQ039);
  _EQ039 =  _LC1_E28 & !_LC3_D44
         #  _LC3_D44 &  row0;

-- Node name is ':581' 
-- Equation name is '_LC5_E28', type is buried 
_LC5_E28 = LCELL( _EQ040);
  _EQ040 = !_LC2_D44 &  _LC3_E28
         #  _LC2_D44 &  row8;

-- Node name is ':584' 
-- Equation name is '_LC2_E28', type is buried 
_LC2_E28 = LCELL( _EQ041);
  _EQ041 = !_LC1_D44 &  _LC5_E28
         #  cond0 &  _LC1_D44;



Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontroler.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:08
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:11


Memory Allocated
-----------------

Peak memory allocated during compilation  = 41,866K
