Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 07/09/2002 17:39:09

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


OUTPUTCONTROLERM


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

outputcontrolerm
      EPF10K10TC144-3      81     9      0    0         0  %    88       15 %

User Pins:                 81     9      0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

***** Logic for device 'outputcontrolerm' compiled without errors.




Device: EPF10K10TC144-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** ERROR SUMMARY **

Info: Chip 'outputcontrolerm' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                                         
                                                                                         
                                                            R   R   R R R       R R      
                c     c         o           r   c     c     E c E r E E E       E E   c  
                o   r o         u           o   o G r o c V S o S o S S S     c S S   o  
                n c o l c G     t   V   c c w G n N o n o C E l E w E E E V c o E E   n  
                d o w _ o N r r b r C c o o _ N d D w d l C R _ R _ R R R C o l R R r d  
                _ n _ 2 n D o o u o C o n l 2 D _ I _ _ _ I V 2 V 2 V V V C l _ V V o _  
                2 d 2 1 d I w w s w I l d 1 1 I 2 N 2 2 2 N E 1 E 1 E E E I 1 2 E E w 2  
                6 5 3 2 7 O 2 1 6 7 O 6 4 3 5 O 2 T 0 0 0 T D 5 D 2 D D D O 2 3 D D 6 3  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GNDIO 
    VCCINT |  6                                                                         103 | GNDINT 
   outbus4 |  7                                                                         102 | row8 
   outbus0 |  8                                                                         101 | col4 
     col15 |  9                                                                         100 | col_24 
      col7 | 10                                                                          99 | row_24 
     row12 | 11                                                                          98 | col_211 
    row_27 | 12                                                                          97 | col0 
   outbus7 | 13                                                                          96 | row0 
      col8 | 14                                                                          95 | row15 
     GNDIO | 15                                                                          94 | VCCIO 
    GNDINT | 16                                                                          93 | VCCINT 
     row10 | 17                                                                          92 | col2 
   outbus5 | 18                                                                          91 | row3 
     row13 | 19                             EPF10K10TC144-3                              90 | col11 
    row_25 | 20                                                                          89 | row_22 
   row_213 | 21                                                                          88 | row5 
      col5 | 22                                                                          87 | row11 
   outbus3 | 23                                                                          86 | row_211 
     VCCIO | 24                                                                          85 | GNDIO 
    VCCINT | 25                                                                          84 | GNDINT 
     col14 | 26                                                                          83 | col9 
   cond_21 | 27                                                                          82 | cond6 
      row9 | 28                                                                          81 | row_214 
     reset | 29                                                                          80 | row_21 
     row14 | 30                                                                          79 | row_29 
    row_26 | 31                                                                          78 | cond1 
      col1 | 32                                                                          77 | ^MSEL0 
   outbus1 | 33                                                                          76 | ^MSEL1 
      #TMS | 34                                                                          75 | VCCINT 
  ^nSTATUS | 35                                                                          74 | ^nCONFIG 
   cond_24 | 36                                                                          73 | RESERVED 
           |      38  40  42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  _| 
            \   37  39  41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71   | 
             \--------------------------------------------------------------------------- 
                c c c G c c c r V c o r c G c V V c r c G G c c V c c c R G R c R c V R  
                o o o N o o o o C o u o o N o C C s o o N N o o C o o o E N E o E o C E  
                l n l D n n n w C l t w l D l C C   w l D D l l C l l l S D S l S n C S  
                _ d 3 I d d d 4 I _ b _ _ I _ I I   _ _ I I _ 1 I _ _ _ E I E _ E d I E  
                2 _   O 2 0 _   O 2 u 2 2 O 2 N N   2 2 N N 2 0 O 2 2 2 R O R 2 R 3 O R  
                7 2         2     2 s 1 1   5 T T   8 8 T T 1     9 1 1 V   V 6 V     V  
                  7         5       2 0                     0       3 4 E   E   E     E  
                                                                        D   D   D     D  
                                                                                         
                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A13      8/ 8(100%)   5/ 8( 62%)   3/ 8( 37%)    0/2    0/2      18/22( 81%)   
A16      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
A20      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
A24      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
B15      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
B16      8/ 8(100%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      17/22( 77%)   
B21      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
C14      8/ 8(100%)   4/ 8( 50%)   6/ 8( 75%)    1/2    0/2       1/22(  4%)   
C15      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
C20      8/ 8(100%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2      17/22( 77%)   
C21      8/ 8(100%)   6/ 8( 75%)   7/ 8( 87%)    1/2    0/2       4/22( 18%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                            84/96     ( 87%)
Total logic cells used:                         88/576    ( 15%)
Total embedded cells used:                       0/24     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 3.27/4    ( 81%)
Total fan-in:                                 288/2304    ( 12%)

Total input pins required:                      81
Total input I/O cell registers required:         0
Total output pins required:                      9
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     88
Total flipflops required:                        4
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         0/ 576   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   8   0   0   0   8   0   0   0   8     32/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   8   0   0   0   0   8   0   0   0     24/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   8   0   0   0   0   8   8   0   0   0     32/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   8   8  16  16   0   0   0  16  16   0   0   8     88/0  



Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  97      -     -    A    --      INPUT                0    0    0    1  col0
  32      -     -    C    --      INPUT                0    0    0    1  col1
  92      -     -    B    --      INPUT                0    0    0    1  col2
  39      -     -    -    21      INPUT                0    0    0    1  col3
 101      -     -    A    --      INPUT                0    0    0    1  col4
  22      -     -    B    --      INPUT                0    0    0    1  col5
 133      -     -    -    17      INPUT                0    0    0    1  col6
  10      -     -    A    --      INPUT                0    0    0    1  col7
  14      -     -    A    --      INPUT                0    0    0    1  col8
  83      -     -    C    --      INPUT                0    0    0    1  col9
  60      -     -    -    12      INPUT                0    0    0    1  col10
  90      -     -    B    --      INPUT                0    0    0    1  col11
 114      -     -    -    04      INPUT                0    0    0    1  col12
 131      -     -    -    15      INPUT                0    0    0    1  col13
  26      -     -    C    --      INPUT                0    0    0    1  col14
   9      -     -    A    --      INPUT                0    0    0    1  col15
 124      -     -    -    --      INPUT                0    0    0    1  col_20
  49      -     -    -    14      INPUT                0    0    0    1  col_21
  46      -     -    -    17      INPUT                0    0    0    1  col_22
 113      -     -    -    03      INPUT                0    0    0    1  col_23
 100      -     -    A    --      INPUT                0    0    0    1  col_24
  51      -     -    -    13      INPUT                0    0    0    1  col_25
  68      -     -    -    07      INPUT                0    0    0    1  col_26
  37      -     -    -    23      INPUT                0    0    0    1  col_27
  56      -     -    -    --      INPUT                0    0    0    1  col_28
  62      -     -    -    11      INPUT                0    0    0    1  col_29
  59      -     -    -    12      INPUT                0    0    0    1  col_210
  98      -     -    A    --      INPUT                0    0    0    1  col_211
 141      -     -    -    22      INPUT                0    0    0    1  col_212
  63      -     -    -    11      INPUT                0    0    0    1  col_213
  64      -     -    -    10      INPUT                0    0    0    1  col_214
 121      -     -    -    10      INPUT                0    0    0    1  col_215
  42      -     -    -    19      INPUT                0    0    0    1  cond0
  78      -     -    C    --      INPUT                0    0    0    1  cond1
  41      -     -    -    20      INPUT                0    0    0    1  cond2
  70      -     -    -    05      INPUT                0    0    0    1  cond3
 132      -     -    -    16      INPUT                0    0    0    1  cond4
 143      -     -    -    24      INPUT                0    0    0    1  cond5
  82      -     -    C    --      INPUT                0    0    0    1  cond6
 140      -     -    -    21      INPUT                0    0    0    1  cond7
 125      -     -    -    --      INPUT                0    0    0    1  cond_20
  27      -     -    C    --      INPUT                0    0    0    1  cond_21
 128      -     -    -    13      INPUT                0    0    0    1  cond_22
 109      -     -    -    01      INPUT                0    0    0    1  cond_23
  36      -     -    -    24      INPUT                0    0    0    1  cond_24
  43      -     -    -    18      INPUT                0    0    0    1  cond_25
 144      -     -    -    24      INPUT                0    0    0    1  cond_26
  38      -     -    -    22      INPUT                0    0    0    1  cond_27
  54      -     -    -    --      INPUT  G             0    0    0    0  cs
  96      -     -    A    --      INPUT                0    0    0    1  row0
 137      -     -    -    19      INPUT                0    0    0    1  row1
 138      -     -    -    20      INPUT                0    0    0    1  row2
  91      -     -    B    --      INPUT                0    0    0    1  row3
  44      -     -    -    18      INPUT                0    0    0    1  row4
  88      -     -    B    --      INPUT                0    0    0    1  row5
 110      -     -    -    01      INPUT                0    0    0    1  row6
 135      -     -    -    18      INPUT                0    0    0    1  row7
 102      -     -    A    --      INPUT                0    0    0    1  row8
  28      -     -    C    --      INPUT                0    0    0    1  row9
  17      -     -    B    --      INPUT                0    0    0    1  row10
  87      -     -    B    --      INPUT                0    0    0    1  row11
  11      -     -    A    --      INPUT                0    0    0    1  row12
  19      -     -    B    --      INPUT                0    0    0    1  row13
  30      -     -    C    --      INPUT                0    0    0    1  row14
  95      -     -    A    --      INPUT                0    0    0    1  row15
 126      -     -    -    --      INPUT                0    0    0    1  row_20
  80      -     -    C    --      INPUT                0    0    0    1  row_21
  89      -     -    B    --      INPUT                0    0    0    1  row_22
 142      -     -    -    23      INPUT                0    0    0    1  row_23
  99      -     -    A    --      INPUT                0    0    0    1  row_24
  20      -     -    B    --      INPUT                0    0    0    1  row_25
  31      -     -    C    --      INPUT                0    0    0    1  row_26
  12      -     -    A    --      INPUT                0    0    0    1  row_27
  55      -     -    -    --      INPUT                0    0    0    1  row_28
  79      -     -    C    --      INPUT                0    0    0    1  row_29
  48      -     -    -    15      INPUT                0    0    0    1  row_210
  86      -     -    B    --      INPUT                0    0    0    1  row_211
 119      -     -    -    08      INPUT                0    0    0    1  row_212
  21      -     -    B    --      INPUT                0    0    0    1  row_213
  81      -     -    C    --      INPUT                0    0    0    1  row_214
 130      -     -    -    14      INPUT                0    0    0    1  row_215


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   8      -     -    A    --        TRI                0    1    0    0  outbus0
  33      -     -    C    --        TRI                0    1    0    0  outbus1
  47      -     -    -    16        TRI                0    1    0    0  outbus2
  23      -     -    B    --        TRI                0    1    0    0  outbus3
   7      -     -    A    --        TRI                0    1    0    0  outbus4
  18      -     -    B    --        TRI                0    1    0    0  outbus5
 136      -     -    -    19        TRI                0    1    0    0  outbus6
  13      -     -    A    --        TRI                0    1    0    0  outbus7
  29      -     -    C    --     OUTPUT                0    1    0    0  reset


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      7     -    C    14       DFFE   +            0    3    0   13  state3 (:91)
   -      2     -    C    21       DFFE   +            0    4    0   14  state2 (:92)
   -      3     -    C    14       DFFE   +            0    3    0   13  state1 (:93)
   -      6     -    C    14       DFFE   +            0    3    0   13  state0 (:94)
   -      8     -    C    14       AND2                0    4    0    8  :252
   -      5     -    C    14       AND2                0    4    0    8  :264
   -      2     -    C    14       AND2                0    4    0    8  :276
   -      6     -    C    21       AND2                0    4    0    9  :288
   -      3     -    C    21       AND2                0    4    0    9  :300
   -      1     -    C    14       AND2                0    4    0    9  :312
   -      4     -    C    21       AND2                0    4    0    9  :324
   -      7     -    C    21        OR2        !       0    4    0    9  :336
   -      8     -    C    21        OR2        !       0    4    0    9  :348
   -      5     -    C    21        OR2        !       0    4    0    9  :360
   -      1     -    C    21        OR2                0    4    0    1  :387
   -      4     -    C    14        OR2        !       0    4    1    0  :604
   -      2     -    A    13        OR2                2    2    0    1  :762
   -      1     -    A    16        OR2                1    2    0    1  :774
   -      2     -    A    16        OR2                1    2    0    1  :786
   -      3     -    A    16        OR2                1    2    0    1  :798
   -      4     -    A    16        OR2                1    2    0    1  :810
   -      5     -    A    16        OR2                1    2    0    1  :822
   -      7     -    A    16        OR2                1    2    0    1  :834
   -      8     -    A    16        OR2                1    2    0    1  :846
   -      6     -    A    16        OR2                1    2    1    0  :858
   -      3     -    A    13        OR2                2    2    0    1  :867
   -      1     -    C    20        OR2                1    2    0    1  :870
   -      3     -    C    20        OR2                1    2    0    1  :873
   -      4     -    C    20        OR2                1    2    0    1  :876
   -      5     -    C    20        OR2                1    2    0    1  :879
   -      6     -    C    20        OR2                1    2    0    1  :882
   -      7     -    C    20        OR2                1    2    0    1  :885
   -      8     -    C    20        OR2                1    2    0    1  :888
   -      2     -    C    20        OR2                1    2    1    0  :891
   -      7     -    A    13        OR2                2    2    0    1  :900
   -      1     -    B    15        OR2                1    2    0    1  :903
   -      3     -    B    15        OR2                1    2    0    1  :906
   -      4     -    B    15        OR2                1    2    0    1  :909
   -      5     -    B    15        OR2                1    2    0    1  :912
   -      6     -    B    15        OR2                1    2    0    1  :915
   -      7     -    B    15        OR2                1    2    0    1  :918
   -      8     -    B    15        OR2                1    2    0    1  :921
   -      2     -    B    15        OR2                1    2    1    0  :924
   -      1     -    A    13        OR2                2    2    0    1  :933
   -      2     -    A    20        OR2                1    2    0    1  :936
   -      3     -    A    20        OR2                1    2    0    1  :939
   -      4     -    A    20        OR2                1    2    0    1  :942
   -      5     -    A    20        OR2                1    2    0    1  :945
   -      6     -    A    20        OR2                1    2    0    1  :948
   -      7     -    A    20        OR2                1    2    0    1  :951
   -      8     -    A    20        OR2                1    2    0    1  :954
   -      1     -    A    20        OR2                1    2    1    0  :957
   -      4     -    A    13        OR2                2    2    0    1  :966
   -      1     -    B    21        OR2                1    2    0    1  :969
   -      2     -    B    21        OR2                1    2    0    1  :972
   -      3     -    B    21        OR2                1    2    0    1  :975
   -      4     -    B    21        OR2                1    2    0    1  :978
   -      5     -    B    21        OR2                1    2    0    1  :981
   -      6     -    B    21        OR2                1    2    0    1  :984
   -      8     -    B    21        OR2                1    2    0    1  :987
   -      7     -    B    21        OR2                1    2    1    0  :990
   -      5     -    A    13        OR2                2    2    0    1  :999
   -      1     -    B    16        OR2                1    2    0    1  :1002
   -      3     -    B    16        OR2                1    2    0    1  :1005
   -      4     -    B    16        OR2                1    2    0    1  :1008
   -      5     -    B    16        OR2                1    2    0    1  :1011
   -      6     -    B    16        OR2                1    2    0    1  :1014
   -      7     -    B    16        OR2                1    2    0    1  :1017
   -      8     -    B    16        OR2                1    2    0    1  :1020
   -      2     -    B    16        OR2                1    2    1    0  :1023
   -      6     -    A    13        OR2                2    2    0    1  :1032
   -      1     -    C    15        OR2                1    2    0    1  :1035
   -      2     -    C    15        OR2                1    2    0    1  :1038
   -      3     -    C    15        OR2                1    2    0    1  :1041
   -      4     -    C    15        OR2                1    2    0    1  :1044
   -      5     -    C    15        OR2                1    2    0    1  :1047
   -      6     -    C    15        OR2                1    2    0    1  :1050
   -      7     -    C    15        OR2                1    2    0    1  :1053
   -      8     -    C    15        OR2                1    2    1    0  :1056
   -      8     -    A    13        OR2                2    2    0    1  :1065
   -      1     -    A    24        OR2                1    2    0    1  :1068
   -      3     -    A    24        OR2                1    2    0    1  :1071
   -      4     -    A    24        OR2                1    2    0    1  :1074
   -      5     -    A    24        OR2                1    2    0    1  :1077
   -      6     -    A    24        OR2                1    2    0    1  :1080
   -      7     -    A    24        OR2                1    2    0    1  :1083
   -      8     -    A    24        OR2                1    2    0    1  :1086
   -      2     -    A    24        OR2                1    2    1    0  :1089


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      30/ 96( 31%)     0/ 48(  0%)    21/ 48( 43%)   13/16( 81%)      3/16( 18%)     0/16(  0%)
B:      21/ 96( 21%)     0/ 48(  0%)    16/ 48( 33%)   12/16( 75%)      2/16( 12%)     0/16(  0%)
C:      20/ 96( 20%)     0/ 48(  0%)    12/ 48( 25%)   12/16( 75%)      2/16( 12%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
11:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
12:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
13:     10/24( 41%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
14:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
15:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
16:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
17:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
18:      3/24( 12%)     3/4( 75%)      0/4(  0%)       0/4(  0%)
19:      3/24( 12%)     2/4( 50%)      1/4( 25%)       0/4(  0%)
20:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
21:      5/24( 20%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
22:      5/24( 20%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
23:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
24:      3/24( 12%)     3/4( 75%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       12         cs


Device-Specific Information:c:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt
outputcontrolerm

** EQUATIONS **

col0     : INPUT;
col1     : INPUT;
col2     : INPUT;
col3     : INPUT;
col4     : INPUT;
col5     : INPUT;
col6     : INPUT;
col7     : INPUT;
col8     : INPUT;
col9     : INPUT;
col10    : INPUT;
col11    : INPUT;
col12    : INPUT;
col13    : INPUT;
col14    : INPUT;
col15    : INPUT;
col_20   : INPUT;
col_21   : INPUT;
col_22   : INPUT;
col_23   : INPUT;
col_24   : INPUT;
col_25   : INPUT;
col_26   : INPUT;
col_27   : INPUT;
col_28   : INPUT;
col_29   : INPUT;
col_210  : INPUT;
col_211  : INPUT;
col_212  : INPUT;
col_213  : INPUT;
col_214  : INPUT;
col_215  : INPUT;
cond0    : INPUT;
cond1    : INPUT;
cond2    : INPUT;
cond3    : INPUT;
cond4    : INPUT;
cond5    : INPUT;
cond6    : INPUT;
cond7    : INPUT;
cond_20  : INPUT;
cond_21  : INPUT;
cond_22  : INPUT;
cond_23  : INPUT;
cond_24  : INPUT;
cond_25  : INPUT;
cond_26  : INPUT;
cond_27  : INPUT;
cs       : INPUT;
row0     : INPUT;
row1     : INPUT;
row2     : INPUT;
row3     : INPUT;
row4     : INPUT;
row5     : INPUT;
row6     : INPUT;
row7     : INPUT;
row8     : INPUT;
row9     : INPUT;
row10    : INPUT;
row11    : INPUT;
row12    : INPUT;
row13    : INPUT;
row14    : INPUT;
row15    : INPUT;
row_20   : INPUT;
row_21   : INPUT;
row_22   : INPUT;
row_23   : INPUT;
row_24   : INPUT;
row_25   : INPUT;
row_26   : INPUT;
row_27   : INPUT;
row_28   : INPUT;
row_29   : INPUT;
row_210  : INPUT;
row_211  : INPUT;
row_212  : INPUT;
row_213  : INPUT;
row_214  : INPUT;
row_215  : INPUT;

-- Node name is 'outbus0' 
-- Equation name is 'outbus0', type is output 
outbus0  = TRI(_LC2_A24, GLOBAL( cs));

-- Node name is 'outbus1' 
-- Equation name is 'outbus1', type is output 
outbus1  = TRI(_LC8_C15, GLOBAL( cs));

-- Node name is 'outbus2' 
-- Equation name is 'outbus2', type is output 
outbus2  = TRI(_LC2_B16, GLOBAL( cs));

-- Node name is 'outbus3' 
-- Equation name is 'outbus3', type is output 
outbus3  = TRI(_LC7_B21, GLOBAL( cs));

-- Node name is 'outbus4' 
-- Equation name is 'outbus4', type is output 
outbus4  = TRI(_LC1_A20, GLOBAL( cs));

-- Node name is 'outbus5' 
-- Equation name is 'outbus5', type is output 
outbus5  = TRI(_LC2_B15, GLOBAL( cs));

-- Node name is 'outbus6' 
-- Equation name is 'outbus6', type is output 
outbus6  = TRI(_LC2_C20, GLOBAL( cs));

-- Node name is 'outbus7' 
-- Equation name is 'outbus7', type is output 
outbus7  = TRI(_LC6_A16, GLOBAL( cs));

-- Node name is 'reset' 
-- Equation name is 'reset', type is output 
reset    = !_LC4_C14;

-- Node name is ':94' = 'state0' 
-- Equation name is 'state0', location is LC6_C14, type is buried.
state0   = DFFE( _EQ001, GLOBAL( cs),  VCC,  VCC,  VCC);
  _EQ001 = !state0 & !state3
         # !state0 & !state1 & !state2;

-- Node name is ':93' = 'state1' 
-- Equation name is 'state1', location is LC3_C14, type is buried.
state1   = DFFE( _EQ002, GLOBAL( cs),  VCC,  VCC,  VCC);
  _EQ002 =  state0 & !state1 & !state3
         # !state0 &  state1 & !state3
         #  state0 & !state1 & !state2;

-- Node name is ':92' = 'state2' 
-- Equation name is 'state2', location is LC2_C21, type is buried.
state2   = DFFE( _EQ003, GLOBAL( cs),  VCC,  VCC,  VCC);
  _EQ003 =  _LC1_C21 & !_LC5_C21 & !_LC7_C21 & !_LC8_C21;

-- Node name is ':91' = 'state3' 
-- Equation name is 'state3', location is LC7_C14, type is buried.
state3   = DFFE( _EQ004, GLOBAL( cs),  VCC,  VCC,  VCC);
  _EQ004 =  state0 &  state1 &  state2 & !state3
         # !state1 & !state2 &  state3;

-- Node name is ':252' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = LCELL( _EQ005);
  _EQ005 =  state0 & !state1 & !state2 &  state3;

-- Node name is ':264' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ006);
  _EQ006 = !state0 & !state1 & !state2 &  state3;

-- Node name is ':276' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = LCELL( _EQ007);
  _EQ007 =  state0 &  state1 &  state2 & !state3;

-- Node name is ':288' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ008);
  _EQ008 = !state0 &  state1 &  state2 & !state3;

-- Node name is ':300' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ009);
  _EQ009 =  state0 & !state1 &  state2 & !state3;

-- Node name is ':312' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = LCELL( _EQ010);
  _EQ010 = !state0 & !state1 &  state2 & !state3;

-- Node name is ':324' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ011);
  _EQ011 =  state0 &  state1 & !state2 & !state3;

-- Node name is ':336' 
-- Equation name is '_LC7_C21', type is buried 
!_LC7_C21 = _LC7_C21~NOT;
_LC7_C21~NOT = LCELL( _EQ012);
  _EQ012 =  state3
         # !state1
         #  state2
         #  state0;

-- Node name is ':348' 
-- Equation name is '_LC8_C21', type is buried 
!_LC8_C21 = _LC8_C21~NOT;
_LC8_C21~NOT = LCELL( _EQ013);
  _EQ013 =  state2
         #  state1
         #  state3
         # !state0;

-- Node name is ':360' 
-- Equation name is '_LC5_C21', type is buried 
!_LC5_C21 = _LC5_C21~NOT;
_LC5_C21~NOT = LCELL( _EQ014);
  _EQ014 =  state3
         #  state1
         #  state2
         #  state0;

-- Node name is ':387' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ015);
  _EQ015 =  _LC3_C21
         #  _LC6_C21
         #  _LC4_C21
         #  _LC1_C14;

-- Node name is ':604' 
-- Equation name is '_LC4_C14', type is buried 
!_LC4_C14 = _LC4_C14~NOT;
_LC4_C14~NOT = LCELL( _EQ016);
  _EQ016 =  state2
         #  state0
         # !state1
         # !state3;

-- Node name is ':762' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ017);
  _EQ017 =  col_215 &  _LC5_C14
         #  col_27 &  _LC8_C14;

-- Node name is ':774' 
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = LCELL( _EQ018);
  _EQ018 =  _LC2_A13 & !_LC2_C14
         #  _LC2_C14 &  row_27;

-- Node name is ':786' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ019);
  _EQ019 =  _LC1_A16 & !_LC6_C21
         #  _LC6_C21 &  row_215;

-- Node name is ':798' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = LCELL( _EQ020);
  _EQ020 =  _LC2_A16 & !_LC3_C21
         #  cond_27 &  _LC3_C21;

-- Node name is ':810' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ021);
  _EQ021 = !_LC1_C14 &  _LC3_A16
         #  col7 &  _LC1_C14;

-- Node name is ':822' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ022);
  _EQ022 =  _LC4_A16 & !_LC4_C21
         #  col15 &  _LC4_C21;

-- Node name is ':834' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ023);
  _EQ023 =  _LC5_A16 & !_LC7_C21
         #  _LC7_C21 &  row7;

-- Node name is ':846' 
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ024);
  _EQ024 =  _LC7_A16 & !_LC8_C21
         #  _LC8_C21 &  row15;

-- Node name is ':858' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ025);
  _EQ025 = !_LC5_C21 &  _LC8_A16
         #  cond7 &  _LC5_C21;

-- Node name is ':867' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ026);
  _EQ026 =  col_214 &  _LC5_C14
         #  col_26 &  _LC8_C14;

-- Node name is ':870' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = LCELL( _EQ027);
  _EQ027 = !_LC2_C14 &  _LC3_A13
         #  _LC2_C14 &  row_26;

-- Node name is ':873' 
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ028);
  _EQ028 =  _LC1_C20 & !_LC6_C21
         #  _LC6_C21 &  row_214;

-- Node name is ':876' 
-- Equation name is '_LC4_C20', type is buried 
_LC4_C20 = LCELL( _EQ029);
  _EQ029 =  _LC3_C20 & !_LC3_C21
         #  cond_26 &  _LC3_C21;

-- Node name is ':879' 
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = LCELL( _EQ030);
  _EQ030 = !_LC1_C14 &  _LC4_C20
         #  col6 &  _LC1_C14;

-- Node name is ':882' 
-- Equation name is '_LC6_C20', type is buried 
_LC6_C20 = LCELL( _EQ031);
  _EQ031 = !_LC4_C21 &  _LC5_C20
         #  col14 &  _LC4_C21;

-- Node name is ':885' 
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ032);
  _EQ032 =  _LC6_C20 & !_LC7_C21
         #  _LC7_C21 &  row6;

-- Node name is ':888' 
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = LCELL( _EQ033);
  _EQ033 =  _LC7_C20 & !_LC8_C21
         #  _LC8_C21 &  row14;

-- Node name is ':891' 
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = LCELL( _EQ034);
  _EQ034 = !_LC5_C21 &  _LC8_C20
         #  cond6 &  _LC5_C21;

-- Node name is ':900' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ035);
  _EQ035 =  col_213 &  _LC5_C14
         #  col_25 &  _LC8_C14;

-- Node name is ':903' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ036);
  _EQ036 = !_LC2_C14 &  _LC7_A13
         #  _LC2_C14 &  row_25;

-- Node name is ':906' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ037);
  _EQ037 =  _LC1_B15 & !_LC6_C21
         #  _LC6_C21 &  row_213;

-- Node name is ':909' 
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ038);
  _EQ038 =  _LC3_B15 & !_LC3_C21
         #  cond_25 &  _LC3_C21;

-- Node name is ':912' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = LCELL( _EQ039);
  _EQ039 = !_LC1_C14 &  _LC4_B15
         #  col5 &  _LC1_C14;

-- Node name is ':915' 
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = LCELL( _EQ040);
  _EQ040 = !_LC4_C21 &  _LC5_B15
         #  col13 &  _LC4_C21;

-- Node name is ':918' 
-- Equation name is '_LC7_B15', type is buried 
_LC7_B15 = LCELL( _EQ041);
  _EQ041 =  _LC6_B15 & !_LC7_C21
         #  _LC7_C21 &  row5;

-- Node name is ':921' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = LCELL( _EQ042);
  _EQ042 =  _LC7_B15 & !_LC8_C21
         #  _LC8_C21 &  row13;

-- Node name is ':924' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ043);
  _EQ043 = !_LC5_C21 &  _LC8_B15
         #  cond5 &  _LC5_C21;

-- Node name is ':933' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ044);
  _EQ044 =  col_212 &  _LC5_C14
         #  col_24 &  _LC8_C14;

-- Node name is ':936' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ045);
  _EQ045 =  _LC1_A13 & !_LC2_C14
         #  _LC2_C14 &  row_24;

-- Node name is ':939' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ046);
  _EQ046 =  _LC2_A20 & !_LC6_C21
         #  _LC6_C21 &  row_212;

-- Node name is ':942' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ047);
  _EQ047 =  _LC3_A20 & !_LC3_C21
         #  cond_24 &  _LC3_C21;

-- Node name is ':945' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ048);
  _EQ048 = !_LC1_C14 &  _LC4_A20
         #  col4 &  _LC1_C14;

-- Node name is ':948' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ049);
  _EQ049 = !_LC4_C21 &  _LC5_A20
         #  col12 &  _LC4_C21;

-- Node name is ':951' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ050);
  _EQ050 =  _LC6_A20 & !_LC7_C21
         #  _LC7_C21 &  row4;

-- Node name is ':954' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ051);
  _EQ051 =  _LC7_A20 & !_LC8_C21
         #  _LC8_C21 &  row12;

-- Node name is ':957' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ052);
  _EQ052 = !_LC5_C21 &  _LC8_A20
         #  cond4 &  _LC5_C21;

-- Node name is ':966' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ053);
  _EQ053 =  col_211 &  _LC5_C14
         #  col_23 &  _LC8_C14;

-- Node name is ':969' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = LCELL( _EQ054);
  _EQ054 = !_LC2_C14 &  _LC4_A13
         #  _LC2_C14 &  row_23;

-- Node name is ':972' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ055);
  _EQ055 =  _LC1_B21 & !_LC6_C21
         #  _LC6_C21 &  row_211;

-- Node name is ':975' 
-- Equation name is '_LC3_B21', type is buried 
_LC3_B21 = LCELL( _EQ056);
  _EQ056 =  _LC2_B21 & !_LC3_C21
         #  cond_23 &  _LC3_C21;

-- Node name is ':978' 
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = LCELL( _EQ057);
  _EQ057 = !_LC1_C14 &  _LC3_B21
         #  col3 &  _LC1_C14;

-- Node name is ':981' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ058);
  _EQ058 =  _LC4_B21 & !_LC4_C21
         #  col11 &  _LC4_C21;

-- Node name is ':984' 
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ059);
  _EQ059 =  _LC5_B21 & !_LC7_C21
         #  _LC7_C21 &  row3;

-- Node name is ':987' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = LCELL( _EQ060);
  _EQ060 =  _LC6_B21 & !_LC8_C21
         #  _LC8_C21 &  row11;

-- Node name is ':990' 
-- Equation name is '_LC7_B21', type is buried 
_LC7_B21 = LCELL( _EQ061);
  _EQ061 = !_LC5_C21 &  _LC8_B21
         #  cond3 &  _LC5_C21;

-- Node name is ':999' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ062);
  _EQ062 =  col_210 &  _LC5_C14
         #  col_22 &  _LC8_C14;

-- Node name is ':1002' 
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = LCELL( _EQ063);
  _EQ063 = !_LC2_C14 &  _LC5_A13
         #  _LC2_C14 &  row_22;

-- Node name is ':1005' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ064);
  _EQ064 =  _LC1_B16 & !_LC6_C21
         #  _LC6_C21 &  row_210;

-- Node name is ':1008' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ065);
  _EQ065 =  _LC3_B16 & !_LC3_C21
         #  cond_22 &  _LC3_C21;

-- Node name is ':1011' 
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ066);
  _EQ066 = !_LC1_C14 &  _LC4_B16
         #  col2 &  _LC1_C14;

-- Node name is ':1014' 
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = LCELL( _EQ067);
  _EQ067 = !_LC4_C21 &  _LC5_B16
         #  col10 &  _LC4_C21;

-- Node name is ':1017' 
-- Equation name is '_LC7_B16', type is buried 
_LC7_B16 = LCELL( _EQ068);
  _EQ068 =  _LC6_B16 & !_LC7_C21
         #  _LC7_C21 &  row2;

-- Node name is ':1020' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ069);
  _EQ069 =  _LC7_B16 & !_LC8_C21
         #  _LC8_C21 &  row10;

-- Node name is ':1023' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = LCELL( _EQ070);
  _EQ070 = !_LC5_C21 &  _LC8_B16
         #  cond2 &  _LC5_C21;

-- Node name is ':1032' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ071);
  _EQ071 =  col_29 &  _LC5_C14
         #  col_21 &  _LC8_C14;

-- Node name is ':1035' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ072);
  _EQ072 = !_LC2_C14 &  _LC6_A13
         #  _LC2_C14 &  row_21;

-- Node name is ':1038' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ073);
  _EQ073 =  _LC1_C15 & !_LC6_C21
         #  _LC6_C21 &  row_29;

-- Node name is ':1041' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ074);
  _EQ074 =  _LC2_C15 & !_LC3_C21
         #  cond_21 &  _LC3_C21;

-- Node name is ':1044' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ075);
  _EQ075 = !_LC1_C14 &  _LC3_C15
         #  col1 &  _LC1_C14;

-- Node name is ':1047' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ076);
  _EQ076 =  _LC4_C15 & !_LC4_C21
         #  col9 &  _LC4_C21;

-- Node name is ':1050' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ077);
  _EQ077 =  _LC5_C15 & !_LC7_C21
         #  _LC7_C21 &  row1;

-- Node name is ':1053' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ078);
  _EQ078 =  _LC6_C15 & !_LC8_C21
         #  _LC8_C21 &  row9;

-- Node name is ':1056' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ079);
  _EQ079 = !_LC5_C21 &  _LC7_C15
         #  cond1 &  _LC5_C21;

-- Node name is ':1065' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ080);
  _EQ080 =  col_28 &  _LC5_C14
         #  col_20 &  _LC8_C14;

-- Node name is ':1068' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ081);
  _EQ081 = !_LC2_C14 &  _LC8_A13
         #  _LC2_C14 &  row_20;

-- Node name is ':1071' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = LCELL( _EQ082);
  _EQ082 =  _LC1_A24 & !_LC6_C21
         #  _LC6_C21 &  row_28;

-- Node name is ':1074' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = LCELL( _EQ083);
  _EQ083 =  _LC3_A24 & !_LC3_C21
         #  cond_20 &  _LC3_C21;

-- Node name is ':1077' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ084);
  _EQ084 = !_LC1_C14 &  _LC4_A24
         #  col0 &  _LC1_C14;

-- Node name is ':1080' 
-- Equation name is '_LC6_A24', type is buried 
_LC6_A24 = LCELL( _EQ085);
  _EQ085 = !_LC4_C21 &  _LC5_A24
         #  col8 &  _LC4_C21;

-- Node name is ':1083' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = LCELL( _EQ086);
  _EQ086 =  _LC6_A24 & !_LC7_C21
         #  _LC7_C21 &  row0;

-- Node name is ':1086' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = LCELL( _EQ087);
  _EQ087 =  _LC7_A24 & !_LC8_C21
         #  _LC8_C21 &  row8;

-- Node name is ':1089' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = LCELL( _EQ088);
  _EQ088 = !_LC5_C21 &  _LC8_A24
         #  cond0 &  _LC5_C21;



Project Informationc:\documents and settings\default\my documents\imdl\cpld\mouse code\outputcontrolerm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:02
   Partitioner                            00:00:01
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:09


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,974K
