;------------------------------------------
;Project Name:  323 Acceleration.asm
;Description:	Test Single Channel PWM 16Bit Up/Down Counter Acceleration
;Author:		Max Koessick
;Date;			July 26, 2003
;Revision:		1.0  Working 16Bit PWM
;				1.a
;------------------------------------------
;Use 3.69MHz clock
;Use Prescaler =/64 ->57.6kHz = T=~17uS
;8bit PWM Up/Down counts to $FF->17uS*FF=4.423ms = T(PWM)/2
;@1.0ms, 4.423-1.0/2=3.923ms
;	solve(.003923=.000017x,x)->x=226=$E2 *Servo Left*
;@1.5ms, 4.423-1.5/2=3.673ms
;	solve(.003673=.000017x,x)->x=212=$D4 *Servo Neutral*
;@2.0ms, 4.423-2.0/2=3.423ms
;	solve(.003423=.000017x,x)->x=197=$C5 *Servo Right*

.nolist
.include "m323def.inc" 		; Default Include file for ATMega128
.list						; Do not include the "m323def.inc" in the .lst file

;Interrupt Service Vector Addresses

.org $0000
	rjmp RESET				; Reset Vector
.org INT0addr
	rjmp IntV0
.org INT1addr
	rjmp IntV1
.org INT2addr
	rjmp IntV2

;-------------------------------------------
;Register Definitions
;-------------------------------------------

.def mpr   		=r16		; Temporary Register
.def mpr2		=r17		; Old Speed Register
.def newspd		=r18		; New Speed Register

.equ Neu		=$d7
.equ Rt			=$e2
.equ Lft		=$c5
;Initialization

RESET:

;-----Setting Stackpointer----------------------------------------
	ldi		MPR,low(RAMEND)			; Set stackptr to ram end
	out		SPL,MPR
	ldi 	MPR, high(RAMEND)
	out 	SPH, MPR

;-----Set Port Directions----------------------------------------
		
	ldi		mpr,$f0
	out		DDRD,mpr			; Set PORTC to output

	ser		mpr
	out		ddrc,mpr
	out   	portc,mpr

;-----Enable 16Bit PWM Counter------------------------------------

	ldi		mpr,Neu				; Test value *Servo Neutral*
	out		OCR1AL,mpr			; Load OCR1AL with value for 1.0 ms pulse in a T=8.8ms

	ldi		mpr,0b11000001		; Bit7:6 -> Inverted PWM
								; Bit5:4 -> Disable OC1B 
								; Bit3;2 -> FOC =n/a
								; Bit1:0 -> 8Bit PWM mode
	out		TCCR1A,mpr

	ldi		mpr,0b00000011		; Bit7 -> Input Noise Canceler Disabled
								; Bit6 -> Input Capter Edge Select n/a
								; Bit5:4 -> Unsused
								; Bit3 -> Clear on Compare Match Disabled
								; Bit2:0 -> Prescale = /64
	out		TCCR1B,mpr
;------Enable External Interupts-----------------------------------

	in		mpr,MCUCSR
	andi	mpr,0b10111111		; Clear the INT2 Sense Control Bit -> Falling Edge triggered
	out		MCUCSR,mpr

	in		mpr,MCUCR
	andi	mpr,0b11111111		; Set ISC1:0 Sense Control bits [3:0] -> Falling Edge 
	out		MCUCR,mpr

	ldi		mpr,0b11110000		; Set IVCE bit
	out		GICR,mpr


;------------------------------------------------------------------
	
	sei							; Enable Interupts


mainloop:
	rjmp 	mainloop

IntV0:  						;Accelerate

	ldi		mpr,$55
	out		portc,mpr

	ldi		mpr,NEU				; Test value *Servo right*

ADDONE:
	subi	mpr,1
	cpi		mpr,$d0
	breq	END
	out		OCR1AL,mpr			; Load OCR1AL with value for 1.0 ms pulse in a T=8.8ms

	ldi		XL,$ff
	ldi		XH,$ff
DLYLP1:
	sbiw	XH:XL,1
	brne	DLYLP1

	rjmp	Addone
End:
	reti

IntV1:	
	ldi		mpr,$aa
	out		portc,mpr
	ldi		mpr,neu				; Test value *Servo neutral*
	out		OCR1AL,mpr			; Load OCR1AL with value for 1.5 ms pulse in a T=8.8ms
	reti

IntV2:
	ldi		mpr,$77
	out		portc,mpr
	ldi		mpr,$C5				; Test value *Servo left*
	out		OCR1AL,mpr			; Load OCR1AL with value for 2.0 ms pulse in a T=8.8ms
	reti
