;------------------------------------------
;Project Name:  323 PWM Test.asm
;Description:	Test Single Channel PWM 8Bit Up/Down Counter
;Author:		Max Koessick
;Date;			July 6, 2003
;Revision:		1.0
;------------------------------------------
;Use 3.69MHz clock
;Use Prescaler =/64 ->57.6kHz = T=~17uS
;8bit PWM Up/Down counts to $FF->17uS*FF=4.423ms = T(PWM)/2
;@1.0ms, 4.423-1.0/2=3.923ms
;	solve(.003923=.000017x,x)->x=226=$E2 *Servo Left*
;@1.5ms, 4.423-1.5/2=3.673ms
;	solve(.003673=.000017x,x)->x=212=$D4 *Servo Neutral*
;@2.0ms, 4.423-2.0/2=3.423ms
;	solve(.003423=.000017x,x)->x=197=$C5 *Servo Right*

.nolist
.include "m323def.inc" 		; Default Include file for ATMega128
.list						; Do not include the "m323def.inc" in the .lst file

;Interrupt Service Vector Addresses

.org $0000
	rjmp RESET				; Reset Vector

;-------------------------------------------
;Register Definitions
;-------------------------------------------

.def mpr   		=r16		; Temporary Register

;Initialization

RESET:

;-----Setting Stackpointer----------------------------------------
	ldi		MPR,low(RAMEND)			; Set stackptr to ram end
	out		SPL,MPR
	ldi 	MPR, high(RAMEND)
	out 	SPH, MPR

;-----Set Port Directions----------------------------------------
		
	ldi		mpr,(1<<PB3)
	out		DDRB,mpr			; Set PORTC to output

	ldi		mpr,(1<<PD7)
	out		DDRD,mpr


	ldi		mpr,$c9				; Test value *Servo Neutral*
	out		OCR0,mpr			; Load OCR0 with value for 1.0 ms pulse in a T=8.8ms
	ldi		mpr,$a0		; Test value *Servo Neutral*
	out		OCR2,mpr

	ldi		mpr,0b01110011		; Bit7 -> FOC2 force Output Compare = n/a
								; Bit6 -> PWM0 Enables PWM output 
								; Bit5:4 -> Set on match upcount, clear on match downcount (11)
								; Bit3 -> CTC0 No clear on match
								; Bit2:0 -> Prescale = /64
	out		TCCR0,mpr
	out		TCCR2,mpr			

mainloop:
	rjmp 	mainloop