
AVRASM ver. 1.57  C:\Documents and Settings\Max\My Documents\EEL5666 IMDL\CommandRegRead\CommandRegRead.asm Wed Jul 02 23:16:38 2003


         
         
         ;-----------------------------------------------------------------
         ; Name:			128 TWI.asm
         ; Description:	ATMega128 Two Wire Interface (IC2) Test Program
         ;				Interfaces SRF09 Sonar Range Finder to IC2 Bus
         
         ; Author:		Max Koessick
         ; Class:		EEL5666C, Intelligent Machine Design Lab
         ; Date:			June 28, 2003
         ; Revision		1.a
         ; Changes to Date:
         ;				6/28/03 First Revision
         ;-----------------------------------------------------------------
         
          .nolist								; Do not include in .lst file
         ; Interrupt service vectors
         
          .org $0000
000000 c000      	rjmp Reset						; Reset vector
         ;.org INT0addr
         ;	rjmp IntV0						; INT0 vector (ext. interrupt from pin D0)	
         ;.org INT1addr	
         ;	rjmp IntV1						; INT1 vector (ext. interrupt from pin D1)
         ;.org INT2addr		
         ;	rjmp IntV2						; INT2 vector (ext. interrupt from pin D2)
         
         
         	
         ;-----------------------------------------------------------------
         ; Register defines for main loop
         ;-----------------------------------------------------------------
         
         
          .def		mpr		=r16			; defines multipurpose register
          .def		mpr2	=r17			; multipurpose register 2
          .def		ECHOL	=r18
          .def		ECHOH	=r19
          .def		ErrorReg=r20
          .def		mpr3	=r21
         
         
         ; Equate statements
          .equ		start		= $08		; Start Condition 
          .equ		Rep_start	= $10		; Repeated Start Condition Message
          .equ		MT_SLA_ACK	= $18		; Master Transmitter Slave Address Acknowledge
          .equ		MT_DATA_ACK = $28		; Master Transmitter Data Acknowledge
          .equ		MT_DATA_NACK= $30		; Master Transmitter Data Not Acknowledge
          .equ		MR_SLA_ACK	= $40		; Master Receiver Slave Address Acknowledge
          .equ		MR_SLA_NACK	= $48		; Master Receiver Slave Address Acknowledge
          .equ		MR_DATA_ACK = $50		; Master Receiver Data Acknowlede
          .equ		MR_DATA_NACK= $58		; Master Receiver Data Not Acknowledge
          .equ		W			= 0			; Write Bit
          .equ		R			= 1			; Read Bit
          .equ		SLA			= $E0		; Slave Address of Sonar Ranger SRF08
          .equ		Inches		= $50		; Return result in Inches
          .equ		CommandReg	= $00		; SRF08 Command Register
         ;-----------------------------------------------------------------
         ; Reset vector
         ;-----------------------------------------------------------------
         
          Reset:
         ;-----Setting Stackpointer----------------------------------------
000001 ef0f      	ldi		MPR,low(RAMEND)			; Set stackptr to ram end
000002 bf0d      	out		SPL,MPR
000003 e100      	ldi 	MPR, high(RAMEND)
000004 bf0e      	out 	SPH, MPR
         
         ;-----Set Port Directions-----------------------------------------
000005 ef0f      	ser		mpr						; Set TEMP to $FF to...
         
000006 bb04      	out 	DDRC,mpr
000007 ef0f      	ser		mpr
000008 bb05      	out		PORTC,mpr				; Lights off
         
000009 e001      	ldi		mpr,$01
00000a bb01      	out		DDRD,mpr				;Set PD0 as output and PD1 as input
         
00000b e001      	ldi		mpr,(1<<PD0)
00000c bb02      	out		PORTD,mpr
         
         ;-----------------------------------------------------------------
         
00000d 940c 00b5 	jmp		test
         
00000f 2744      	clr 	ErrorReg
         	
         
         ; Set TWIBitRate for fclk=16Mhz
         
000010 e00c      	ldi		mpr,12					;400Khz=16MHz/(16+2*12) See Datasheet Pg202
000011 9300 0070 	sts		TWBR,mpr
         
000013 e000      	ldi		mpr,$00
000014 9300 0071 	sts		TWSR,mpr
         
         ; Initialize TWCR Register
         
000016 ec04      	ldi 		MPR, (1<<TWINT)|(1<<TWEA) | (1<<TWEN);
000017 9300 0074 	sts	 		TWCR,MPR 			; Send START condition
000019 9478      	sei								; set interrupts active
         			
         ; **MASTER TRANSMITTER*****
         
         
00001a ea04      	ldi 		MPR, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)|(0<<TWSTO);
00001b 9300 0074 	sts	 		TWCR,MPR 				; Send START condition
         
         
          WAIT1: 
00001d 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
00001f ff07      	sbrs 		MPR,TWINT 			; the START condition has been transmitted
000020 cffc      	rjmp 		WAIT1
         
000021 9100 0071 	lds 		MPR,TWSR 			; Check value of TWI Status Register.
000023 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
000024 3008      	cpi 		MPR,START 			; If status different from START go to ERROR
000025 f011      	breq		NEXT1
000026 940c 008b 	jmp			ERROR1
         		
         ;***SLAVE ADDRESS***
         
          NEXT1:
000028 e004      	ldi 		MPR,(0<<TWINT) | (1<<TWEN)
000029 9300 0074 	sts	 		TWCR,MPR 
00002b ee00      	ldi 		MPR,SLA+W			; Load SLA+W into TWDR Register
00002c 9300 0073 	sts	 		TWDR,MPR
00002e e804      	ldi 		MPR,(1<<TWINT) | (1<<TWEN)|(0<<TWSTA)|(0<<TWSTO)
00002f 9300 0074 	sts	 		TWCR,MPR 			; Clear TWINT bit in TWCR to start transmission
         									; of address
          WAIT2: 
000031 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
000033 ff07      	sbrs 		MPR,TWINT 			; SLA+W has been transmitted, and ACK/NACK has
000034 cffc      	rjmp 		WAIT2 				; been received
         
000035 9100 0071 	lds 		MPR,TWSR 			; Check value of TWI Status Register. If status
000037 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
000038 3108      	cpi 		MPR,MT_SLA_ACK 		; different from MT_SLA_ACK, go to ERROR
000039 f011      	breq		NEXT2
00003a 940c 008d 	jmp			ERROR2
         
         ;***COMMAND REGISTER***
         
          NEXT2:
00003c e004      	ldi 		MPR,(0<<TWINT) | (1<<TWEN)
00003d 9300 0074 	sts	 		TWCR,MPR 
00003f e000      	ldi 		MPR,CommandReg 		; Load data (CommandReg Address) into TWDR
         									; Register
000040 9300 0073 	sts 		TWDR,MPR
000042 e804      	ldi 		MPR,(1<<TWINT) | (1<<TWEN)|(0<<TWSTA)|(0<<TWSTO)
000043 9300 0074 	sts 		TWCR,MPR 			; Clear TWINT bit in TWCR to start transmission
         									; of data
          WAIT3: 
         
000045 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
000047 ff07      	sbrs 		MPR,TWINT 			; data has been transmitted, and ACK/NACK has
000048 cffc      	rjmp 		WAIT3 				; been received
         
000049 9100 0071 	lds 		MPR,TWSR 			; Check value of TWI Status Register. If status
00004b 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
00004c 3208      	cpi 		MPR,MT_DATA_ACK 	; different from MT_DATA_ACK, go to ERROR
00004d f011      	breq		NEXT3
00004e 940c 008f 	jmp			ERROR3
         
          NEXT3:
000050 e904      	ldi 		mpr,(1<<TWINT)|(1<<TWSTO)|(1<<TWEN)|(0<<TWSTA)
000051 9300 0074 	sts			TWCR,mpr
         ;Wait for last transmission to end
         
          Check1:
000053 9100 0074 	lds			mpr,TWCR
000055 7100      	andi		mpr,0b00010000		; Check to see that no transmission is going on
000056 f7e1      	brne		Check1
         
         ;Send Repeated Start
          NEXT7:
000057 ea04      	ldi 		MPR,(1<<TWINT) | (1<<TWSTA) | (1<<TWEN)|(0<<TWSTO)
000058 9300 0074 	sts	 		TWCR,MPR 			; Send REP_START condition
          WAIT8:
00005a 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
00005c ff07      	sbrs 		MPR,TWINT 			; the START condition has been transmitted
00005d cffc      	rjmp 		WAIT8
         	
00005e 9100 0071 	lds 		MPR,TWSR 			; Check value of TWI Status Register. If status
         									; different from START, go to ERROR
000060 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
000061 3008      	cpi 		MPR,START 		
000062 f011      	breq 		NEXT8
000063 940c 0099 	JMP			ERROR8
         
         
         ;***SLAVE ADDRESS+READ***
          NEXT8:
000065 e004      	ldi 		MPR,(0<<TWINT) | (1<<TWEN)
000066 9300 0074 	sts	 		TWCR,MPR
000068 ee01      	ldi 		MPR,SLA+R 			; Load SLA+R into TWDR Register
         
000069 9300 0073 	sts	 		TWDR,MPR
00006b ec04      	ldi 		MPR,(1<<TWINT) | (1<<TWEN)| (1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)
00006c 9300 0074 	sts	 		TWCR,MPR 			; Clear TWINT bit in TWCR to start transmission
         									; of SLA+R
          WAIT9:
00006e 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
000070 ff07      	sbrs 		MPR,TWINT 			; SLA+R has been transmitted, and ACK/NACK has
000071 cffc      	rjmp 		WAIT9 				; been received
         
000072 9100 0071 	lds 		MPR,TWSR			; Check value of TWI Status Register. If status
         									; different from MR_SLA_ACK, go to ERROR
000074 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
000075 3400      	cpi 		MPR,MR_SLA_ACK 		
000076 f521      	brne 		ERROR9
         
         
         ;Get last data Byte
         
000077 e804      	ldi			MPR,(1<<TWINT) | (1<<TWEN)|(0<<TWSTA)|(0<<TWSTO)
000078 9300 0074 	sts	 		TWCR,MPR 			; Clear TWINT bit in TWCR to start reception of
         									; data. Not setting TWEA causes NACK to be
         									; returned after reception of next data byte
         									; receive last data byte. Signal this to Slave
         									; by returning NACK
          WAIT11:
00007a 9100 0074 	lds 		MPR,TWCR			; Wait for TWINT Flag set. This indicates that
00007c ff07      	sbrs 		MPR,TWINT 			; data has been received and NACK returned
00007d cffc      	rjmp 		WAIT11
         
00007e 9100 0071 	lds 		MPR,TWSR 			; Check value of TWI Status Register. If status
000080 7f08      	andi		MPR,$F8				; Mask Prescaler Bits
000081 3508      	cpi 		MPR,MR_DATA_NACK 	; different from MR_DATA_NACK, go to ERROR
000082 f4e1      	brne 		ERROR11
         
000083 9120 0073 	lds			ECHOL,TWDR 			; Input received data from TWDR.
         
         ;Issue Stop 
         
000085 e904      	ldi 		MPR,(1<<TWINT) | (1<<TWSTO) | (1<<TWEN)|(0<<TWSTA)
000086 9300 0074 	sts	 		TWCR,MPR 			; Send STOP signal
         
         
          mainloop:
000088 9520      	com			ECHOL
000089 bb25      	out			PORTC,ECHOL
00008a cffd      	rjmp		mainloop
         
          ERROR1:
00008b e041      	ldi			ErrorReg,$01
00008c c014      	rjmp		output
          ERROR2:
00008d e042      	ldi			ErrorReg,$02
00008e c012      	rjmp		output
          ERROR3:
00008f e043      	ldi			ErrorReg,$03
000090 c010      	rjmp		output
          ERROR4:
000091 e044      	ldi			ErrorReg,$04
000092 c00e      	rjmp		output
          ERROR5:
000093 e045      	ldi			ErrorReg,$05
000094 c00c      	rjmp		output
          ERROR6:
000095 e046      	ldi			ErrorReg,$06
000096 c00a      	rjmp		output
          ERROR7:
000097 e047      	ldi			ErrorReg,$07
000098 c008      	rjmp		output
          ERROR8:
000099 e048      	ldi			ErrorReg,$08
00009a c006      	RJMP		output
          ERROR9:
00009b e049      	ldi			ErrorReg,$09
00009c c004      	RJMP		output
          ERROR10:
00009d e04a      	ldi			ErrorReg,$0A
00009e c002      	RJMP		output
          ERROR11:
00009f e04b      	ldi			ErrorReg,$0B
0000a0 c000      	RJMP		output
          Output:
         
         ; Load Contents of TWI Status Register and display on Port C (LEDs)
         
0000a1 9110 0071 	lds 		mpr2,TWSR			; Load the TWSR for Error display
0000a3 2b14      	or			mpr2,errorreg
0000a4 9510      	com			mpr2				; Change to active low LEDs
0000a5 bb15      	out			PORTC,MPR2 
          LOOP1:
0000a6 cfff      	rjmp		loop1
         ; *** 65ms delay while Sonar process data
         ;---------------------------------------------------------------------
          Delay65ms:
         
0000a7 93bf      	push  		XH
0000a8 93af      	push		XL
0000a9 931f      	push		mpr2
         
0000aa efbf      	ldi			XH,$ff
0000ab efaf      	ldi			XL,$ff
0000ac ef1f      	ldi			mpr2,$ff
         
          loop:
0000ad 9711      	sbiw		XH:XL,1
0000ae f7f1      	brne		loop
0000af 951a      	dec			mpr2
0000b0 f7e1      	brne		loop
         
0000b1 911f      	pop 		mpr2
         
0000b2 91af      	pop			XL
0000b3 91bf      	pop			XH
         
0000b4 9508      	ret
         
          Test:
0000b5 e050      	ldi		mpr3,$00
0000b6 bb55      	out		portc,mpr3
          loop2:
0000b7 cfff      	rjmp	loop2
0000b8 9508      	ret
Assembly complete with no errors.
