Project Information                                    c:\pneuman\vhdl\pid.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 03/02/2001 23:10:54

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

pid       EPM7032SLC44-10  10       6        0      6       0           18 %

User Pins:                 10       6        0  



Project Information                                    c:\pneuman\vhdl\pid.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

pid@5                             A1
pid@6                             A2
pid@8                             A3
pid@9                             A4
pid@4                             BASEADD
pid@11                            CSM0
pid@12                            CSM1
pid@14                            CSM2
pid@16                            CSM3
pid@19                            HI0
pid@20                            HI1
pid@21                            HI2
pid@24                            HI3
pid@25                            IRQ
pid@17                            RESET
pid@18                            /RST


Project Information                                    c:\pneuman\vhdl\pid.rpt

** FILE HIERARCHY **



|74138:1|


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

***** Logic for device 'pid' compiled without errors.




Device: EPM7032SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                                         R  R  
                    B                    E  E  
                    A                    S  S  
                    S                    E  E  
                    E                    R  R  
                    A  V  G  G  G  G  G  V  V  
              A  A  D  C  N  N  N  N  N  E  E  
              2  1  D  C  D  D  D  D  D  D  D  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | RESERVED 
      A3 |  8                                38 | #TDO 
      A4 |  9                                37 | RESERVED 
     GND | 10                                36 | RESERVED 
    CSM0 | 11                                35 | VCC 
    CSM1 | 12        EPM7032SLC44-10         34 | RESERVED 
    #TMS | 13                                33 | RESERVED 
    CSM2 | 14                                32 | #TCK 
     VCC | 15                                31 | RESERVED 
    CSM3 | 16                                30 | GND 
   RESET | 17                                29 | RESERVED 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              /  H  H  H  G  V  H  I  R  R  R  
              R  I  I  I  N  C  I  R  E  E  E  
              S  0  1  2  D  C  3  Q  S  S  S  
              T                       E  E  E  
                                      R  R  R  
                                      V  V  V  
                                      E  E  E  
                                      D  D  D  


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     5/16( 31%)  16/16(100%)   0/16(  0%)   6/36( 16%) 
B:    LC17 - LC32     1/16(  6%)   4/16( 25%)   0/16(  0%)   4/36( 11%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            20/32     ( 62%)
Total logic cells used:                          6/32     ( 18%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                    6/32     ( 18%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  4.16
Total fan-in:                                    25

Total input pins required:                      10
Total fast input logic cells required:           0
Total output pins required:                      6
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                      6
Total flipflops required:                        0
Total product terms required:                    6
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   5    (2)  (A)      INPUT               0      0   0    0    0    4    0  A1
   6    (3)  (A)      INPUT               0      0   0    0    0    4    0  A2
   8    (5)  (A)      INPUT               0      0   0    0    0    4    0  A3
   9    (6)  (A)      INPUT               0      0   0    0    0    4    0  A4
   4    (1)  (A)      INPUT               0      0   0    0    0    4    0  BASEADD
  19   (14)  (A)      INPUT               0      0   0    0    0    1    0  HI0
  20   (15)  (A)      INPUT               0      0   0    0    0    1    0  HI1
  21   (16)  (A)      INPUT               0      0   0    0    0    1    0  HI2
  24   (32)  (B)      INPUT               0      0   0    0    0    1    0  HI3
  17   (12)  (A)      INPUT               0      0   0    0    0    1    0  RESET


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  11      7    A     OUTPUT      t        0      0   0    5    0    0    0  CSM0
  12      8    A     OUTPUT      t        0      0   0    5    0    0    0  CSM1
  14     10    A     OUTPUT      t        0      0   0    5    0    0    0  CSM2
  16     11    A     OUTPUT      t        0      0   0    5    0    0    0  CSM3
  25     31    B     OUTPUT      t        0      0   0    4    0    0    0  IRQ
  18     13    A     OUTPUT      t        0      0   0    1    0    0    0  /RST


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                   Logic cells placed in LAB 'A'
        +--------- LC7 CSM0
        | +------- LC8 CSM1
        | | +----- LC10 CSM2
        | | | +--- LC11 CSM3
        | | | | +- LC13 /RST
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'A'
LC      | | | | | | A B |     Logic cells that feed LAB 'A':

Pin
5    -> * * * * - | * - | <-- A1
6    -> * * * * - | * - | <-- A2
8    -> * * * * - | * - | <-- A3
9    -> * * * * - | * - | <-- A4
4    -> * * * * - | * - | <-- BASEADD
17   -> - - - - * | * - | <-- RESET


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC31 IRQ
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B |     Logic cells that feed LAB 'B':

Pin
19   -> * | - * | <-- HI0
20   -> * | - * | <-- HI1
21   -> * | - * | <-- HI2
24   -> * | - * | <-- HI3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           c:\pneuman\vhdl\pid.rpt
pid

** EQUATIONS **

A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
BASEADD  : INPUT;
HI0      : INPUT;
HI1      : INPUT;
HI2      : INPUT;
HI3      : INPUT;
RESET    : INPUT;

-- Node name is 'CSM0' 
-- Equation name is 'CSM0', location is LC007, type is output.
 CSM0    = LCELL( _EQ001 $  VCC);
  _EQ001 = !A1 & !A2 & !A3 & !A4 & !BASEADD;

-- Node name is 'CSM1' 
-- Equation name is 'CSM1', location is LC008, type is output.
 CSM1    = LCELL( _EQ002 $  VCC);
  _EQ002 =  A1 & !A2 & !A3 & !A4 & !BASEADD;

-- Node name is 'CSM2' 
-- Equation name is 'CSM2', location is LC010, type is output.
 CSM2    = LCELL( _EQ003 $  VCC);
  _EQ003 = !A1 &  A2 & !A3 & !A4 & !BASEADD;

-- Node name is 'CSM3' 
-- Equation name is 'CSM3', location is LC011, type is output.
 CSM3    = LCELL( _EQ004 $  VCC);
  _EQ004 =  A1 &  A2 & !A3 & !A4 & !BASEADD;

-- Node name is 'IRQ' 
-- Equation name is 'IRQ', location is LC031, type is output.
 IRQ     = LCELL( _EQ005 $  VCC);
  _EQ005 = !HI0 & !HI1 & !HI2 & !HI3;

-- Node name is '/RST' 
-- Equation name is '/RST', location is LC013, type is output.
 /RST    = LCELL(!RESET $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    c:\pneuman\vhdl\pid.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,838K
