Project Information                                    c:\pneuman\vhdl\pwm.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 01/30/2001 22:17:31

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

pwm       EPM7032SLC44-10  10       17       0      17      0           53 %

User Pins:                 10       17       0  



Project Information                                    c:\pneuman\vhdl\pwm.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

pwm@5                             GATE00
pwm@8                             GATE01
pwm@41                            GATE02
pwm@12                            GATE10
pwm@16                            GATE11
pwm@18                            GATE12
pwm@20                            GATE20
pwm@24                            GATE21
pwm@26                            GATE22
pwm@4                             OUT00
pwm@6                             OUT01
pwm@9                             OUT02
pwm@11                            OUT10
pwm@14                            OUT11
pwm@17                            OUT12
pwm@19                            OUT20
pwm@21                            OUT21
pwm@25                            OUT22
pwm@39                            PA7
pwm@37                            PWM0
pwm@36                            PWM1
pwm@34                            PWM2
pwm@33                            PWM3
pwm@31                            PWM4
pwm@29                            PWM5
pwm@28                            PWM6
pwm@27                            PWM7


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

***** Logic for device 'pwm' compiled without errors.




Device: EPM7032SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff

                                            R  
                                            E  
                 G                       G  S  
              O  A  O                    A  E  
              U  T  U                    T  R  
              T  E  T  V  G  G  G  G  G  E  V  
              0  0  0  C  N  N  N  N  N  0  E  
              1  0  0  C  D  D  D  D  D  2  D  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | PA7 
  GATE01 |  8                                38 | #TDO 
   OUT02 |  9                                37 | PWM0 
     GND | 10                                36 | PWM1 
   OUT10 | 11                                35 | VCC 
  GATE10 | 12        EPM7032SLC44-10         34 | PWM2 
    #TMS | 13                                33 | PWM3 
   OUT11 | 14                                32 | #TCK 
     VCC | 15                                31 | PWM4 
  GATE11 | 16                                30 | GND 
   OUT12 | 17                                29 | PWM5 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              G  O  G  O  G  V  G  O  G  P  P  
              A  U  A  U  N  C  A  U  A  W  W  
              T  T  T  T  D  C  T  T  T  M  M  
              E  2  E  2        E  2  E  7  6  
              1  0  2  1        2  2  2        
              2     0           1     2        
                                               
                                               


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     6/16( 37%)  16/16(100%)   0/16(  0%)   2/36(  5%) 
B:    LC17 - LC32    11/16( 68%)  15/16( 93%)   0/16(  0%)   9/36( 25%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            31/32     ( 96%)
Total logic cells used:                         17/32     ( 53%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                   17/32     ( 53%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  1.00
Total fan-in:                                    17

Total input pins required:                      10
Total fast input logic cells required:           0
Total output pins required:                     17
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     17
Total flipflops required:                        0
Total product terms required:                   17
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4    (1)  (A)      INPUT               0      0   0    0    0    8    0  OUT00
   6    (3)  (A)      INPUT               0      0   0    0    0    1    0  OUT01
   9    (6)  (A)      INPUT               0      0   0    0    0    1    0  OUT02
  11    (7)  (A)      INPUT               0      0   0    0    0    1    0  OUT10
  14   (10)  (A)      INPUT               0      0   0    0    0    1    0  OUT11
  17   (12)  (A)      INPUT               0      0   0    0    0    1    0  OUT12
  19   (14)  (A)      INPUT               0      0   0    0    0    1    0  OUT20
  21   (16)  (A)      INPUT               0      0   0    0    0    1    0  OUT21
  25   (31)  (B)      INPUT               0      0   0    0    0    1    0  OUT22
  39   (19)  (B)      INPUT               0      0   0    0    0    1    0  PA7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   5      2    A     OUTPUT      t        0      0   0    1    0    0    0  GATE00
   8      5    A     OUTPUT      t        0      0   0    1    0    0    0  GATE01
  41     17    B     OUTPUT      t        0      0   0    1    0    0    0  GATE02
  12      8    A     OUTPUT      t        0      0   0    1    0    0    0  GATE10
  16     11    A     OUTPUT      t        0      0   0    1    0    0    0  GATE11
  18     13    A     OUTPUT      t        0      0   0    1    0    0    0  GATE12
  20     15    A     OUTPUT      t        0      0   0    1    0    0    0  GATE20
  24     32    B     OUTPUT      t        0      0   0    1    0    0    0  GATE21
  26     30    B     OUTPUT      t        0      0   0    1    0    0    0  GATE22
  37     21    B     OUTPUT      t        0      0   0    1    0    0    0  PWM0
  36     22    B     OUTPUT      t        0      0   0    1    0    0    0  PWM1
  34     23    B     OUTPUT      t        0      0   0    1    0    0    0  PWM2
  33     24    B     OUTPUT      t        0      0   0    1    0    0    0  PWM3
  31     26    B     OUTPUT      t        0      0   0    1    0    0    0  PWM4
  29     27    B     OUTPUT      t        0      0   0    1    0    0    0  PWM5
  28     28    B     OUTPUT      t        0      0   0    1    0    0    0  PWM6
  27     29    B     OUTPUT      t        0      0   0    1    0    0    0  PWM7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                     Logic cells placed in LAB 'A'
        +----------- LC2 GATE00
        | +--------- LC5 GATE01
        | | +------- LC8 GATE10
        | | | +----- LC11 GATE11
        | | | | +--- LC13 GATE12
        | | | | | +- LC15 GATE20
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'A'
LC      | | | | | | | A B |     Logic cells that feed LAB 'A':

Pin
4    -> - * * * * * | * * | <-- OUT00
39   -> * - - - - - | * - | <-- PA7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC17 GATE02
        | +------------------- LC32 GATE21
        | | +----------------- LC30 GATE22
        | | | +--------------- LC21 PWM0
        | | | | +------------- LC22 PWM1
        | | | | | +----------- LC23 PWM2
        | | | | | | +--------- LC24 PWM3
        | | | | | | | +------- LC26 PWM4
        | | | | | | | | +----- LC27 PWM5
        | | | | | | | | | +--- LC28 PWM6
        | | | | | | | | | | +- LC29 PWM7
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * * * - - - - - - - - | * * | <-- OUT00
6    -> - - - * - - - - - - - | - * | <-- OUT01
9    -> - - - - * - - - - - - | - * | <-- OUT02
11   -> - - - - - * - - - - - | - * | <-- OUT10
14   -> - - - - - - * - - - - | - * | <-- OUT11
17   -> - - - - - - - * - - - | - * | <-- OUT12
19   -> - - - - - - - - * - - | - * | <-- OUT20
21   -> - - - - - - - - - * - | - * | <-- OUT21
25   -> - - - - - - - - - - * | - * | <-- OUT22


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           c:\pneuman\vhdl\pwm.rpt
pwm

** EQUATIONS **

OUT00    : INPUT;
OUT01    : INPUT;
OUT02    : INPUT;
OUT10    : INPUT;
OUT11    : INPUT;
OUT12    : INPUT;
OUT20    : INPUT;
OUT21    : INPUT;
OUT22    : INPUT;
PA7      : INPUT;

-- Node name is 'GATE00' 
-- Equation name is 'GATE00', location is LC002, type is output.
 GATE00  = LCELL( PA7 $  GND);

-- Node name is 'GATE01' 
-- Equation name is 'GATE01', location is LC005, type is output.
 GATE01  = LCELL( OUT00 $  GND);

-- Node name is 'GATE02' 
-- Equation name is 'GATE02', location is LC017, type is output.
 GATE02  = LCELL( OUT00 $  GND);

-- Node name is 'GATE10' 
-- Equation name is 'GATE10', location is LC008, type is output.
 GATE10  = LCELL( OUT00 $  GND);

-- Node name is 'GATE11' 
-- Equation name is 'GATE11', location is LC011, type is output.
 GATE11  = LCELL( OUT00 $  GND);

-- Node name is 'GATE12' 
-- Equation name is 'GATE12', location is LC013, type is output.
 GATE12  = LCELL( OUT00 $  GND);

-- Node name is 'GATE20' 
-- Equation name is 'GATE20', location is LC015, type is output.
 GATE20  = LCELL( OUT00 $  GND);

-- Node name is 'GATE21' 
-- Equation name is 'GATE21', location is LC032, type is output.
 GATE21  = LCELL( OUT00 $  GND);

-- Node name is 'GATE22' 
-- Equation name is 'GATE22', location is LC030, type is output.
 GATE22  = LCELL( OUT00 $  GND);

-- Node name is 'PWM0' 
-- Equation name is 'PWM0', location is LC021, type is output.
 PWM0    = LCELL( OUT01 $  GND);

-- Node name is 'PWM1' 
-- Equation name is 'PWM1', location is LC022, type is output.
 PWM1    = LCELL( OUT02 $  GND);

-- Node name is 'PWM2' 
-- Equation name is 'PWM2', location is LC023, type is output.
 PWM2    = LCELL( OUT10 $  GND);

-- Node name is 'PWM3' 
-- Equation name is 'PWM3', location is LC024, type is output.
 PWM3    = LCELL( OUT11 $  GND);

-- Node name is 'PWM4' 
-- Equation name is 'PWM4', location is LC026, type is output.
 PWM4    = LCELL( OUT12 $  GND);

-- Node name is 'PWM5' 
-- Equation name is 'PWM5', location is LC027, type is output.
 PWM5    = LCELL( OUT20 $  GND);

-- Node name is 'PWM6' 
-- Equation name is 'PWM6', location is LC028, type is output.
 PWM6    = LCELL( OUT21 $  GND);

-- Node name is 'PWM7' 
-- Equation name is 'PWM7', location is LC029, type is output.
 PWM7    = LCELL( OUT22 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    c:\pneuman\vhdl\pwm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,228K
