********************************************************************* * SPI EXAMPLE (SLAVE) EEL-3744/4744 EMS * ********************************************************************* *************************************************** * GCPU++ * Send one byte to the master and receive one byte * from the master when the master initiates SPI * transfer. *************************************************** * *************************************************** ** SYMBOL DEFINITIONS *************************************************** *************************************************** STACK EQU $900 SP0CR1 EQU $D0 ; SPI Control Register 1 SP0CR2 EQU $D1 ; SPI Control Register 2 SP0BR EQU $D2 ; SPI Baud Register SP0SR EQU $D3 ; SPI Status Register SP0DR EQU $D5 ; SPI Data Register PORTS EQU $D6 ; Serial Port Registor * ; SPI: Bits 7-4 SS, SCK, MOSI, MISO * ; SCI: Bits 1-0 Tx, Rx DDRS EQU $D7 ;DATA DIRECTION REGISTER RAM EQU $0900 ; Start of RAM STK EQU $0A00 ; User Stack RAMPROG EQU $0970 ; Program space in RAM * MASKS BIT765 EQU %11100000 BIT762 EQU %11000100 BIT7 EQU %10000000 BIT6 EQU %01000000 BIT5 EQU %00100000 BIT4 EQU %00010000 BIT3 EQU %00001000 BIT2 EQU %00000100 BIT543 EQU %00111000 * *************************************************** ** DATA SECTION *************************************************** ORG $FFD8 DC.W SPI_ISR ;SPI INTERRUPT VECTOR ORG RAM DATAM DS.B 1 DATAS DC.B $34 *************************************************** ** MAIN PROGRAM *************************************************** ORG RAMPROG *-------------------------------------------------- * INITIALIZATION *-------------------------------------------------- * INITIALIZE STACK & Registers LDS #STACK * * ENABLE SPI OUTPUTS BSET DDRS BIT4 ;output MISO BCLR DDRS BIT765 ;inputs SS-SCK-MOSI * * INITIALIZE SPI * TURN ON SPI INTERRUPT * SET AS SLAVE; CPHA=1, CPOL=0; /32 CLOCK RATE * Bit7 = Enable SPI Interrupt (SPIE) * Bit6 = Enable SPI system (SPE) * Bit5 = Single slave, so wired-or not needed (SWOM) * Bit4 = Set for master (MSTR) * Bit3 = CPOL=0 (CPOL) * Bit2 = CPHA=1 (CPHA) * Note: MSTR must be set at same time or before SPE BSET SP0CR1 BIT762 BCLR SP0CR1 BIT543 * Set SPI speed (NOT NEEDED FOR THE SLAVE) * LDAA #%101 ;Speed E/64 = E / X * STAA SP0BR ; where X = 2^(SPR+1) * * TURN ON INTERRUPT SYSTEM CLI *-------------------------------------------------- * SEND DATA IN DATAM *-------------------------------------------------- LDAA DATAS STAA SP0DR ;process is NOT initiated here; * ; waits for MASTER to initiates it *-------------------------------------------------- * WAIT FOR INTERRUPTS *-------------------------------------------------- HERE BRA HERE * *************************************************** ** INTERRUPT SERVICE ROUTINE *************************************************** ORG $9C0 SPI_ISR BRCLR SP0SR BIT7, RT_SPI ;IGNORE ILLEGAL * ..INTERRUPT LDAA SP0DR STAA DATAM * * RETURN FROM INTERRUPT RT_SPI RTI