LCD MODULE FAQ Version 35B (September 95) ============== ==========================
LCDs are manufactured by quite a few different companies. Units typically seen in the surplus market come from Densitron, Epson, Hewlett Packard, Optrex, or Sharp. Common configurations are 16, 20, 24, 32, or 40 characters by 1, 2, or 4 lines. This FAQ sheet applies only to LCD modules with Hitachi 44780 or equivalent controllers.
I've been loose with the term LCD here. One can find LCDs at any level of integration from what looks like a glass slide and will need drivers and controller, to a PCB that includes the row and column drivers, to the modules I'm actually talking about which also include an on-board controller (usually a Hitachi HD44780). I'd recommend staying away from modules that do not say they have a controller or otherwise indicate that it's included, such as by describing the character set or noting an ASCII interface. The units to look for are usually called character-type dot matrix LCD modules.
If you're interested in the basic principles behind operation of Liquid Crystal Displays, take a look at Scott M. Bruck's LCD FAQ, which is available from ftp.ee.ualberta.ca as the file /pub/cookbook/faq/LCD2.doc Since his FAQ came first, I've changed the name of this one to the LCD MODULE FAQ.
Most of the modules I've seen use the Hitachi controller. These all use the same interface and memory map. The character set is almost always the same with a mixture of English and Japanese characters, but customized models with different character sets also turn up in the surplus market. Also found are modules with extra segments--fixed numbers or words arranged around the dot matrix display area for extra functions. These extra segments look just like additional 5x7 dot boxes to the controller and can be driven by defining custom characters with appropriate bit patterns to energize these special segments as desired.
References used to generate this version:
My gratitude to correspondents and contributors Chris Abbott, Magnus Andersson, John Edwards, Doug Girling, Frank Hausmann, John Payson, Robert Rolf, Philipp Schaeufele, J. R. Spidell, Frank Vorstenbosch, and Brian Wing. Special thanks and my apologies to any correspondents or contributors whom I might have failed to mention.
The current version will be available on the ftp site ftp.ee.ualberta.ca, as /pub/cookbook/faq/lcd.doc, and will be occasionally posted to alt.comp.hardware.homebuilt, and sci.electronics. It is also available through the World Wide Web at URL: http://www.cen.uiuc.edu/~cburian/lcd.doc
Also, a table of the character set in .gif format (640 x 960, 32K) is at URL: http://www.cen.uiuc.edu/~cburian/chset2.gif
Some definitions:
I originally wrote this frustrated by the terse and
cryptic datasheets manufacturers supply. I refer to it more
often than I write to it. I hope engineers, hobbyists,
students and experimenters find it helpful.
1.0 Sources for Modules
=======================
These are the sources I've seen that are most accessible to the
hobbyist. If you know of more, please email me.
My favorite references are the Optrex databook for dot matrix modules, available from Digikey for $2, and the Amateur Robotics column in the June '94 issue of Nuts & Volts magazine, 430 Princeland Court, Corona, CA 91719.
2.0 Specifications
==================
2.1 Pin Description
-------------------
These numbers are the same no matter the physical arrangement of the pins, (for instance, a row along the top on Optrex units, or a 2x7 .100" center array on the side of Sharp units) on 14-pin units. A reader has noted modules with only 10 pins--designed to be used with 4-bit wide data only.
Pin# Symbol Level Function
1 Vss GND Ground
2 Vcc +5V Module power
3 Vee note1 Liquid crystal drive
4 RS_ H/L Register select, H=data, L=instruction
5 R/W H/L Read/Write, H=read (module->CPU), L=write
(CPU->module)
6 E H/L Enable
7 DB0 note2 Data bit 0 (least significant bit)
8 DB1 "
9 DB2 "
10 DB3 "
11 DB4 "
12 DB5 "
13 DB6 "
14 DB7 "
Backlight drive: If the module has a back light, it will be driven by a pair of pads separate from the interface pads. Check your datasheet for power requirements. Electroluminescent strips often specify around 200VAC at 400Hz from a DC-AC converter driven off the 5V power supply.
NOTE1: On standard modules Vee is between GND and 5V; on temperature extended modules it is between GND and -7V. The potentiometer is the contrast adjustment.
Standard:
+5V ------------*----------- Vcc
|
/
10k to \<---------- Vee
20k pot /
\
|
GND ------------*----------- Vss
Temperature extended model:
+5V ------------------------ Vcc
GND ------------*----------- Vss
|
/
10k to \<---------- Vee
20k pot /
\
|
-7V ------------'
Extended temperature types may also employ fancy temperature correction circuitry to provide automatic contrast adjustment.
For operation over a narrow temperature range (such as always indoors), a pair of resistors can be substituted for the potentiometer. At first, try a 10Kohm resistor between Vcc and Vee, and a 330ohm resistor between Vee and Vss, and adjust from there for optimum contrast.
NOTE2: The data pins DB7-DB0 (or DB7-DB4 when using a 4-bit interface) need to be driven by the CPU for a write, but must be switched to hi-Z (or pulled up with pull-up resistors only) so the module can drive the lines on a read or BUSY FLAG check.
When using a 4-bit wide interface, the most significant nybble is written first (bit7-bit4), then the least significant nybble is written (bit3-bit0) on the next Enable cycle. DB3 to DB0 are left unconnected. The pins have internal pullups, so open- collector drivers may be used with them.
Power consumption: Modules use between 10 and 25mW (2 to 5 mA), not counting the backlight, roughly proportional to number of rows and columns.
Be careful when hooking power to the module. Reversing +5V and GND will destroy the unit. Carefully examine your datasheet to correctly identify Pin 1.
2.2 Character Set
-----------------
None of the standard ASCII control codes [chr(1)-chr(31), chr(127)] are implemented.
Standard ASCII is used for chr(32)
The lower case characters do not have decenders. This is because
some LCD's (those with 5x7 dots or 5x8 dots) would chop off the
bottom. Lower case characters with decenders appear near the top
of the character table for use on modules which have 5x11 dot
matrices. You can access them readily by adding 128
(<10000000b>, 80x) if you want decenders and have a 5x11 dot unit
that will properly display them.
Eight user-defined characters are displayed by chr(0) through
chr(7), and redundantly with chr(8) through chr(15). These are
sometimes used to implement a comma and lower case characters g,
j, p, q, and y with a decender into the cursor row on 5x8 units.
Hitachi character set table downloadable through the WWW:
2.3 Instruction Set
Binary data from bit7 to bit 0. If using a 4-bit interface,
bit7-bit4 of data are sent first, then bit3-bit0, on sucessive
enable cycles. No delay is required between these cycles (except
that the minimum E time (450ns) and TcycE time (1us) must be
met).
2.3.1 Write Operations _
RS=0 (except as noted), R/W=0, command/data from CPU to LCD on
bit7 to bit0.
2.3.2 Read Operations _
RS as noted, R/W=1, bit7 to bit0 output from LCD to CPU.
Execution times: Clear display 1.64ms; home cursor 40 us to
1.64ms depending on how far display is scrolled; all others 40us,
except read busy flag which is complete in a single enable cycle
(or two cycles in 4-bit mode), and character generator ram reads and
writes which should be separated by 120us delays. These execution
times mean that after an operation, the CPU must do Busy Flag checks
until the BF (bit 7) is 0, or, when the connection to the module
from the CPU is write-only, wait more than the execution time before
the next operation. These are maximum execution times, some units
(in particular those with 5x11 dot matrices) will execute some
instructions faster.
WRITE:
2.5 Memory map
Character generator RAM appears to reside at locations 64-127 and
display RAM seems to be at locations 128-255. This is an
artifact of the control scheme. They are actually separate non-
contiguous blocks of RAM.
2.5.1 Custom Characters
The display has 64 bytes of CG RAM, which supports 8
user-definable characters, each defined as a 5X8 character in an
8X8 block. The 5X8 region is right-justified. Note that in 5X10
matrix mode, only 4 user-defined characters are supported, using
11 bytes each.
Where "x" is the base address for the character: CG0=0, CG1=8,
CG2=16, CG3=24, CG4=32, CG5=40, CG6=48, CG7=56.
As you can see in the above figure, each byte of CG data
represents 1 row of pixels in the character, with D0 being the
rightmost pixel, and D4 being the leftmost (the upper 3 bits are
not displayed). The first address for a character is the topmost
row, while the 7th is the bottom. (The 8th is ORed with the
cursor underbar). A '1' in any pixel position becomes a dark
pixel on the display.
CG RAM occupies a separate address space from the data display
(DD) RAM. One must set the (first) CG address before writing any
CG data. Each write automatically increments/decrements the CG
address pointer to the next location. Remember to set the
display back to DD addressing mode before trying to write
characters to be displayed.
As an example, we'll define character #3 to be the above symbol
by first reading the DD address, writing the CG address to the
start of the character's RAM, writing the successive rows of
pixel data, then restoring the addressing mode back to DD
addressing (which requires the DD address we saved at the
beginning.
NB. There should be a 120 uSec delay between successive reads or
writes.
(Section 2.5.1 by Doug Girling)
2.5.2 Addressing Display RAM
In the list below, "line 1" is the topmost line, and "line n" is
the bottommost line. On each line, the leftmost character has
the lowest address, and addresses increase to the right. Also,
DD RAM addresses are shown without the 80h mode bit set.
The full 128 bytes of display RAM exist no matter how many
characters appear on the display. These extra bytes can be typed
on when display window scrolling is enabled, or they can be used
to store other information--external data RAM for the CPU, if you
like.
2.6 Initialization
Modules with Hitachi controllers will properly self-initialize if
Vcc rises from 0 to 4.5v in a period between .1mS and 10mS. I
suppose an RC circuit would be needed to keep powerup rise time
as slow as .1ms, so the manual initialization will be required in
most applications. If you do use auto-initialization, it will
come up in this mode: 8-bit interface, 1/8 duty cycle (1 line
mode), 5x7 font, cursor increment right, no shift. On most
displays, you want to switch to 1/16 duty cycle (2 line mode)
because for all but the 20x1, there are two logical lines as the
controller sees it. If you have an 5x11-size character dot matrix
module, you'll want to switch to the 5x10 font as well (the 11th
line is the cursor).
2.6.1 Initialization for 8-bit Operation
NOTE: Remember to turn the display back on and set up the cursor
as desired with an On/Off Control command.
2.6.2 Initialization for 4-bit operation:
The module powers up in 8-bit mode. The initial startup
instructions are sent in 8-bit mode, with the lower four bits
(which are not connected) of each instruction as don't cares.
After the fourth instruction, which switches the module to 4-bit
operation, the control bytes are sent on consecutive enable
cycles (no delay is required between nybbles). Most significant
is sent first, followed immediately by least significant nybble.
NOTE: Remember to turn the display back on and set up the cursor
as desired with an On/Off Control command.
3.0 Interfacing
3.1 Manual test circuit
NOTE: Extended temperature range modules need the non-grounded
end of the potentiometer tied to -7VDC instead of +5VDC.
3.2 Interfacing to a CPU Bus
These modules use an interface like those in Motorola (68xx) and
MOS Technology (65xx) systems. R/W on the module can come from
the R/W line on the CPU, which is set up about the same time as
the address, while RS can be selected by the low order address
line A0. Select Enable by ANDing the output from your address
decoding and the E clock. Address decoding can be done with a
magnitude comparator like the 74LS688, or if you have address
space to spare, with partial address decode like running A13-A14
into a 74LS138 3-to-8 demux, or just the inverse of the high order
address line (hogging a big chunk of address space).
Because Intel (e.g., 8080, 8085, 8048) and Zilog (e.g., Z80) CPUs
use separate read and write lines, and they are not set up ahead
of time, R/W as well as RS must be set via address lines. Then
the Enable signal may be generated from (NOT(/RD AND /WR)) AND
PSEN):
Using the data bus method limits CPU clock speed because of the
tDDR read delay and the TcycE and PWEH requirements of the
Hitachi controller.
(Section 3.2 by Doug Girling)
3.3 Interfacing to a CPU Port
In the case where a direct bus interface is not desired, or is
impractical (e.g., many microcontrollers don't provide an
external data/address bus, or do so at the expense of reassigning
too many pins), the LCD module can be connected via an I/O port.
Whether you use a 4-bit or an 8-bit interface, those port pins
driving the LCD's data lines must be bidirectional if you wish to
read from the LCD. Remember too that you'll have to write your
code to switch the port's data direction bits whenever you switch
from reading to writing or visa versa. If you don't expect to
ever be reading back from the LCD, you can conserve resources by
grounding R/W, saving a pin, and thus using digital outputs
instead of bidirectional ports.
You may be able to eliminate the need for a software-generated
enable (E) signal if the particular port you are using
automatically generates a handshake strobe. In practical terms,
most ports only generate a stobe on output, and expect a strobe
on input, so this approach is most likely applicable to
write-only configurations.
3.3.1 4-Bit Port Interface
Another interface is to drive the module in 4-bit mode using 7
I/O bits from a port.
First, put the most significant nybble on P7-P4, and the
appropriate R/W and RS signals on P3 and P2, and P1 low. Then
toggle P1 high. Then toggle P1 low again. Then put the least
significant nybble on P7-P4, toggle P1 high, toggle P1 low.
Forty microseconds later, you can send the next character.
Sample in-line assembly code, by Jordan Nicol, for implementation
under Dunfield's Micro-C for the Miniboard can be found on ftp
cher.media.mit.edu. It uses port pins PA7-PA3 for 4-bit data and
PC6 and 7 for RS and E.
3.3.2 8-Bit Port Interface
If you have port pins to spare, then an 8-bit interface can be
done with 11 port pins (10 for write only).
3.4.1 Interfacing to the Parallax BASIC STAMP
Sample program with physical hookup described in commented code
can be found on the ftp site wpi.wpi.edu in the /stamp directory.
It's a CPU port hookup as described above. The application also
involves use of a radio control servo.
3.4.2 Interfacing to the Intel 8051 family of microcontrollers
Sample program and schematics appear in the application note
AB-39 in the Intel Embedded Control Applications book for 1988
and probably other years.
3.4.3 Interfacing to the Motorola 68HC11 microcontrollers
Sample programs and circuit descriptions can be found at the
MIT cher.media.mit.edu ftp site. There is the Miniboard hookup
mentioned above, and the use of an LCD module on the 6.270 robot
control boards.
3.4.4 Interfacing to the Microchip PIC microcontrollers
Sample program and schematics appear in the application note
AN587 in the Microchip Embedded Control Handbook for 1994/95.
3.5 Serial Interface
A way to save even more I/O space is to use a serial interface,
requiring just 3 digital output port pins. It uses a shift
register with serial-in, parallel-out, and output latch. This
setup allows the convenient coding of a parallel interface (just
writing the data to the USART transmit buffer) and low pin count
of a serial interface.
The Amateur Robitics column in June '94 Nuts & Volts demonstrated
how to use this technique with the 68hc11's SPI port, using MOSI,
SCK, and /SS. This would be especially handy with a non-
networked 68HC11-based Miniboard single-board computer, which has
MOSI, MISO, SCK, and /SS conveniently routed to the top left
corner where resistor pack 2 goes. The experimenter could put
the contrast potentiometer and latch on a daughterboard mounted
underneath the LCD module.
An alternative with a less expensive shift register has the low
pincount advantage, but requires bit manipulation of port pins:
Save another I/O line with this idea from Robert Rolf:
"On your SPI example, you can free up the latch line by using the
clock line with a diode, pullup, and capacitor. I use the SPI in
normally high mode, rising clock for data bits. 10K pullup, 10nF
to GND, and the clock through diode pulls it low. After all the
bits are shifted in, the RC times-out, and clocks [latches] the
'595."
4.0 LCD Controller chip pinout
NEC UPD44780 LCD Display Controller Pinouts:
PIN DEFINITION
(Section 4.0 by Frank Hausman)
5.0 FTP Sites
* This FAQ.
ftp.ee.ualberta.ca /pub/cookbook/faq/lcd.doc
* LCDFAQ: Liquid Crystal Display physics & principles of operation
by Scott M. Bruck, August 1993.
ftp.ee.ualberta.ca /pub/cookbook/faq/LCD2.doc
* 4-bit interface sample in-line assembly code, by Jordan Nicol,
for implementation under Dunfield's Micro-C for the Miniboard.
It uses port pins PA7-PA3 for 4-bit data and PC6 and PC7 for RS
and E.
ftp cher.media.mit.edu
* Parallax Basic Stamp applications.
wpi.wpi.edu /stamp
9.0 Notice
Trademarks and service marks appearing in this FAQ are the
property of their respective owners. Use this information at
your own risk. I can take no responsibility for damage caused by
errors or omissions in this work. Copyright 1994, 1995 by
Christopher Burian and other contributors. All rights reserved.
Permission is granted to distribute and reproduce this article
provided that it is intact and that it is free of charge (reasonable
copying fees allowed).
Errata, comments, and suggestions are most welcome.
=================================================================
Font Table
---- -----
LSN x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
MSN +---------------------------------------------------------------
0x | cg0 cg1 cg2 cg3 cg4 cg5 cg6 cg7 cg0 cg1 cg2 cg3 cg4 cg5 cg6 cg7
1x | <------------------------- UNDEFINED ------------------------->
2x | ! " # $ % & ' ( ) * + , - . /
3x | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
4x | @ A B C D E F G H I J K L M N O
5x | P Q R S T U V W X Y Z [ (*) ] ^ _
6x | ` a b c d e f g h i j k l m n o
7x | p q r s t u v w x y z { | } --> <--
8x | <------------------------- UNDEFINED ------------------------->
9x | <------------------------- UNDEFINED ------------------------->
Ax | (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*)
Bx | - (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*)
Cx | (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*)
Dx | (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*) (*)
Ex | (*) (*) (*) (*) (*) (*) (*) (g) (*) (*) (j) (*) (*) (*) (*) (*)
Fx | (p) (q) (*) (*) (*) (*) (*) (*) (*) (y) (*) (*) (*) (*) (*) (*)
Notes:
cg0-cg7 user-definable characters
(chr) lower-case character with descenders
(*) see list below:
Hex Decimal Meaning
--- --- -------
5C 92 Yen
A0 160 (blank)
A1 161 katakana
: : :
A5 165 katakana (looks like dot in center)
: : :
DF 223 katakana (looks like degree symbol)
E0 224 LC alpha
E1 225 "a" with umlaut ("a) (German)
E2 226 LC beta (or German es-szet) with
descender
E3 227 LC epsilon
E4 228 LC mu with descender
E5 229 LC sigma
E6 230 LC rho
E7 231 "g" with descender
E8 232 radical (square root sign)
E9 233 "- |" (Katakana?)
EA 234 "j" with descender
EB 235 tiny 3 by 3 'x' in upper left corner
EC 236 cent sign
ED 237 pounds sterling
EE 238 "n" with tilde (Spanish) or overbar
EF 239 "o" with umlaut ("o) (German)
F0 240 "p" with descender
F1 241 "q" with descender
F2 242 LC theta
F3 243 infinity (lazy-8)
F4 244 LC omega
F5 245 "u" with umlaut ("u) (German)
F6 246 UC sigma
F7 247 LC pi
F8 248 "x" with overbar
F9 249 "y" with descender
FA 250 katakana
FB 251 katakana
FC 252 katakana
FD 253 division symbol (:-)
FE 254 (blank)
FF 255 solid black cursor
(Font table by Doug Girling)
http://www.cen.uiuc.edu/~cburian/chset2.gif (640 x 960, 32K)
-------------------
----------------------
* Clear display 00000001
Clears display and returns cursor to home position
(address 0). Execution time: 1.64ms
* Home cursor 0000001x
Returns cursor to home position, returns a shifted display
to original position. Display data RAM (DD RAM) is unaffected.
Execution time: 40us to 1.64ms
x=don't care
* Entry mode set 000001is
Sets cursor move direction and specifies whether or not to
shift display. Execution time: 40us
i=1: increment, i=0: decrement DD RAM address by 1 after
each DD RAM write or read.
s=1: display scrolls in the direction specified by the
"i" bit when the cursor is at the edge of the display
window
* On/off control 00001dcb
Turn display on or off, turn cursor on or off, blink
character at cursor on or off. Execution time: 40us
d=1: display on.
c=1: cursor on
b=1: blink character at cursor position
* Cursor/shift 0001srxx
Move cursor or scroll display without changing display data
RAM. Execution time: 40us
s=1: scroll display, s=0: move cursor.
r=1: to the right, r=0: to the left.
x= don't care
Function set 001dnfxx
Set interface data length, mode, font. Execution time: 40us
d=1: 8-bit interface, d=0: 4-bit interface.
n=1: 1/16 duty, n=0: 1/8 or 1/11 duty (multiplex ratio).
For 2-line displays, this can be thought of as
controlling the number of lines displayed
(n=0: 1-line, n=1: 2-line) except for 1x16
displays which are addressed as if they were
2x8 displays--two 8-character lines side by side.
f=1: 5x11 dots, f=0: 5x8 dots.
Character RAM Address Set 01aaaaaa
To read or write custom characters. Character generator
(CG) RAM occupies a separate address space from the DD RAM. Data
written to, or read from the LCD after this command will be
to/from the CG RAM. Execution time: 40us
aaaaaa: 6-bit CG RAM address to point to.
Display RAM Address Set 1aaaaaaa
Reposition cursor. Display Data (DD) RAM occupies a
separate address space from the CG RAM. Data written to, or read
from the LCD after this command will be to/from the DD RAM.
Execution time: 40us
aaaaaaa: 7-bit DD RAM address to point to.
Write Data to CG or DD RAM dddddddd (RS=1)
Data is written to current cursor position and (DD/CG) RAM
address (which RAM space depends on the most recent CG_RAM_
Address_Set or DD_RAM_Address_Set command). The (DD/CG) RAM
address is incremented/decremented by 1 as determined by the
"entry mode set" command. Execution time: 40us for display write,
120us for character generator ram write
dddddddd: 8-bit character code
---------------------
Read Busy Flag baaaaaaa (RS=0)
Read the status of the busy flag, and the value of the RAM
address currently being pointed at. Execution time: 1 cycle
b=1: busy, b=0: OK to send
aaaaaaa: 7-bit current (DD/CG) RAM address counter (as in
"character RAM address set" or "display RAM address
set").
Read Data from CG or DD RAM zzzzzzzz (RS=1)
Data is read from current (DD/CG) RAM address position, and
the RAM address is automatically incremented/decremented by 1 as
determined by the "entry mode set" command. NOTE that the
display/cursor is not shifted on data reads. Execution time:
40us for display reads, 120us for character generator ram reads
zzzzzzzz: DB lines must be inputs (or pulled high with
pullup resistors) to be driven by the module.
An 8-bit character code will be read back from
LCD RAM.
2.4 Timing
----------
______ _____________________________ ___________
RS ______X_________valid_RS_level______X__________
| |
| |
|<--tAS-->| tAH-->| |<--
______| | | |____________
R/W ______\_________|___R/W_low____|____/_____________
| |
|<----PWEH---->|
| |
|<-------------|-------TcycE----->|
|______________| |_________
E ________________/ \__________________/
tR-->||<-- -->||<--tF
||
|<--tDSW-->||
| -->| |<--tWH
__________________|_______________|________________
D0-D7 __________________X__valid_data___X____________
READ:
______ _____________________________ ___________
RS ______X_________valid_RS_level______X__________
| |
| |
|<--tAS-->| tAH-->| |<--
______|_________|__ _ ____|____|____________
R/W ______/ | R/W high | \_____________
| |
|<----PWEH---->|
| |
|<-------------|-------TcycE----->|
|______________| |_________
E ________________/ \__________________/
tR-->||<-- -->||<--tF
| ||
tDDr-->| |<-- ||
| -->| |<--tRH
___________________|_______________|________________
data ___________________X__valid_data___X____________
TcycE Enable cycle time 1000ns min
Operation cycle time cannot be less than 1 microsecond
PWEH Enable pulse width, high 450ns min
Enable pulse must be at least 450 nanoseconds long, no maximum
length
tRE Enable rise time 25ns max
Enable line must change state (L->H) in less than 25ns
tFE Enable fall time 25ns max
Enable line must change state (H->L) in less than 25ns
tAS Address setup time 140ns min
Register Select and R/W lines must be valid 140ns before
enable pulse arrives
tAH Address hold time 10ns min
RS and R/W must be valid at least 10 ns after enable goes low
tDDR Data delay time 320ns max
When doing a read, the return data will be valid within 320ns
of enable going high
tRH Data hold time, read 20ns min
When doing a read, the return data will be valid at least 20ns
after enable goes low
tDSW Data setup time 195ns min
When doing a write, data on lines bit7-bit0 (or bit7-bit4 in
4-bit mode) must be valid at least 195 ns before enable goes
low
tWH Data hold time, write 10ns min
When doing a write, data on lines must be valid for at least
10ns after enable goes low
Generally, there are no max time requirements on the user except
Enable rise and fall times. An LCD module can be driven with
just toggle switches for data, RS, and R/W, and a debounced
pushbutton on the enable line.
==============
-----------------------
CG Address CG Data
D7-----------D0
x+0 x x x 1 1 1 1 1 *****
x+1 x x x 1 0 0 0 0 *
x+2 x x x 1 0 0 0 1 * *
x+3 x x x 1 1 1 1 1 = *****
x+4 x x x 1 0 0 0 1 * *
x+5 x x x 1 0 0 0 0 *
x+6 x x x 1 0 0 0 0 *
x+7 x x x 0 0 0 0 0 (cursor line)
RS R/W D7----D0
0 1 (baaaaaaa) Read current DD address
0 0 01011000 Set CG RAM address to char #3
(3x8=24=11000b)
1 0 00011111 Write top row of pixels
1 0 00010000 :
1 0 00010001 :
1 0 00011111 :
1 0 00010001 :
1 0 00010000 :
1 0 00010000 Write bottom row of pixels
1 0 00000000 Write cursor row (descender)
0 0 1aaaaaaa Restore DD mode (& address)
----------------------------
16x1 module is arranged as two 8-character lines side by side.
"Line 1" (left) addresses are 00h to 07h
"Line 2" (right) addresses are 40h to 47h
As you write characters to the module, the cursor will
automatically increment until you get to the 9th
character--you have to move the cursor to address 40h
before writing the 9th character on the 1x16 module.
16x2 module is two lines by 16 chars
Line 1 addresses are 00h to 0Fh
Line 2 addresses are 40h to 4Fh
20x1 module
Line 1 addresses are 00h to 13h
20x2 module
Line 1 addresses are 00h to 13h
Line 2 addresses are 40h to 53h
20x4 module
Line 1 addresses are 00h to 13h
Line 2 addresses are 40h to 53h
Line 3 addresses are 14h to 27h
Line 4 addresses are 54h to 67h
40x2 module
Line 1 addresses are 00h to 27h
Line 2 addresses are 40h to 67h
==================
----------------------------------------
-----------------------------------------
===============
-----------------------
__________
| |
GND---*---------| 1 |
< | |
contrast 10K ><--. | |
< | | |
+5V---*---------| 2 |
| | |
`---| 3 |
RS | |
,-----switch------------------------| 4 |
| | |
| +5V-----. GND------| 5 |
| | | |
| # 3.3k pullup resis. | |
| Enable | |\ | |
*--pushbutton--*--| >o-------------| 6 |
| | |/ 74LS04 inverter| |
| --- | |
| --- 1uF cap | |
| | | |
| DB0 GND | |
*---switch--------------------------| 7 |
| | |
| DB1 | |
*---switch--------------------------| 8 |
| | |
~~~ ~~~ ~~~
~~~ ~~~ ~~~
| DB7 | |
*---switch--------------------------| 14 |
| |__________|
|
GND
----------------------------
68xx
65xx LCD
-----. .-----
D0 |--------------------------------| D0
: | : |
D7 |--------------------------------| D7
_ | | _
R/W |--------------------------------| R/W
| .---. |
E |------------------------| | |
| .----------. | & |---| E
A0 |------| | | | |
: | : | (Decode) |------| | `-----
A15 |------| | CS(h)`---'
-----' `----------'
Motorola bus interface
80xx
Z80
_ | .------. _
RD |------*--| S Q |----------------------------------------- R/W
_ | | | |
WR |---*--+--| R |
| | | `------'
| | .---. .---.
| `--| & |O--*-------------------------------| |--- E
`-----| | | .---. R .---. | & |
`---' `--| |O--v^v^v^v--*--| & |O---| |
`---' | `---' `---'
C ===
__|_
/ / /
NB. R & C must be chosen to delay the rising edge of the
enable pulse at least 140ns.
-----------------------------
--------------------------
| .--------
| |
P.7 |<--->| DB7
P.6 |<--->| DB6
P.5 |<--->| DB5
P.4 |<--->| DB4
P.3 |---->| R/W
P.2 |---->| RS
P.1 |---->| E
P.0 |--nc |
| `--------
--------------------------
| .--------
| |
PA0 |<--->| DB0
PA1 |<--->| DB1
PA2 |<--->| DB2
PA3 |<--->| DB3
PA4 |<--->| DB4
PA5 |<--->| DB5
PA6 |<--->| DB6
PA7 |<--->| DB7
| |
PB0 |---->| R/W
PB1 |---->| RS
PB2 |---->| E
PB3 |--nc `--------
PB4 |--nc
PB5 |--nc
PB6 |--nc
PB7 |--nc
|
---------------------------------------------
--------------------------------------------------------------
---------------------------------------------------------
-------------------------------------------------------
--------------------
________________ __________
_____ | 74LS595 | | |
| | QA|-------|DB4 |
|--------|>ser. clock QB|-------|DB5 |
CPU | | QC|-------|DB6 |
OUT |--------|>latch QD|-------|DB7 |
PORT | | QE|-------|RS |
|--------|serial data QF|-------|E |
_____| | QG|--nc | |
10Kohm | QH|--nc | |
pullup | | | |
+5V--^^^---|\Reset | .---|R/W |
.-----|\OE | | |__________|
| |________________| |
GND GND
_____ __________
| | |
|---------------------------------|E |
| ________________ | |
| | 74LS164 | | |
| | QA|-------|DB4 |
|--------|>ser. clock QB|-------|DB5 |
CPU | | QC|-------|DB6 |
OUT | | QD|-------|DB7 |
PORT | | QE|-------|RS |
|--------|serial data QF|--nc | |
_____| | QG|--nc | |
10Kohm | QH|--nc | |
pullup | | | |
+5V--^^^---|\Clear | .---|R/W |
| | | |__________|
|________________| |
GND
==============================
1 SEG 22
2 SEG 21
3 SEG 20
4 SEG 19 666665555555555444444444
5 SEG 18 432109876543210987654321
6 SEG 17 65 40
7 SEG 16 66 39
8 SEG 15 67 38
9 SEG 14 68 37
10 SEG 13 69 36
11 SEG 12 70 35
12 SEG 11 71 34
13 SEG 10 72 33
14 SEG 9 73 UPD44780 TOP 32
15 SEG 8 74 31
16 SEG 7 75 30
17 SEG 6 76 29
18 SEG 5 77 28
19 SEG 4 78 NOTCHED CORNER 27
20 SEG 3 79 /AND POSSIBLE DOT 26
21 SEG 2 80 o 25
22 SEG 1 \ 111111111122222
23 GND 123456789012345678901234
24 OSC 1
25 OSC 2
26 V1
27 V2
28 V3
29 V4
30 V5
31 CL 1
32 CL 2
33 VCC
34 M -
35 D -
36 RS - Reset, assert once
37 R/W* - Hold low for write operation
38 E - Clock low to latch data.
39 DB 0 - The data bus
40 DB 1 -
41 DB 2 -
42 DB 3 -
43 DB 4 -
44 DB 5 -
45 DB 6 -
46 DB 7 -
47 COM 1
48 COM 2
49 COM 3
50 COM 4
51 COM 5
52 COM 6
53 COM 7
54 COM 8
55 COM 9
56 COM 10
57 COM 11
58 COM 12
59 COM 13
60 COM 14
61 COM 15
62 COM 16
63 SEG 40
64 SEG 39
65 SEG 38
66 SEG 37
67 SEG 36
68 SEG 35
69 SEG 34
70 SEG 33
71 SEG 32
72 SEG 31
73 SEG 30
74 SEG 29
75 SEG 28
76 SEG 27
77 SEG 26
78 SEG 25
79 SEG 24
80 SEG 23
=============
==========
Christopher Burian 09/12/95
cburian@uiuc.edu
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